Simulation Results: keymgr

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.80 %
  • code
  • 98.48 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.09 %
  • branch
  • 98.92 %
  • cond
  • 98.15 %
  • toggle
  • 98.56 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.40%
V2S
99.61%
V3
54.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 41.750s 7307.308us 50 50 100.00
random 50 50 100.00
keymgr_random 46.890s 2805.408us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.410s 57.457us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 21.120s 3604.283us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 16.330s 1844.944us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.770s 33.155us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_csr_aliasing 16.330s 1844.944us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 89.410s 10725.342us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 38.620s 5977.170us 50 50 100.00
keymgr_sideload_kmac 21.820s 4172.860us 50 50 100.00
keymgr_sideload_aes 33.550s 9295.225us 50 50 100.00
keymgr_sideload_otbn 21.110s 1574.988us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 36.160s 6498.220us 50 50 100.00
lc_disable 48 50 96.00
keymgr_lc_disable 5.370s 120.903us 48 50 96.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 6.550s 155.094us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 63.100s 16763.519us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 25.240s 3142.646us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 12.540s 994.640us 50 50 100.00
stress_all 47 50 94.00
keymgr_stress_all 391.540s 86477.428us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 1.190s 23.859us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.280s 117.634us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 5.350s 244.358us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 5.350s 244.358us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.410s 57.457us 5 5 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_csr_aliasing 16.330s 1844.944us 5 5 100.00
keymgr_same_csr_outstanding 4.530s 482.842us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.410s 57.457us 5 5 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_csr_aliasing 16.330s 1844.944us 5 5 100.00
keymgr_same_csr_outstanding 4.530s 482.842us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 7.510s 266.375us 20 20 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.230s 494.156us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.230s 494.156us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.230s 494.156us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.230s 494.156us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 17.810s 1106.974us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.510s 266.375us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.230s 494.156us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 89.410s 10725.342us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_random 46.890s 2805.408us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_random 46.890s 2805.408us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.680s 103.352us 20 20 100.00
keymgr_random 46.890s 2805.408us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 48 50 96.00
keymgr_lc_disable 5.370s 120.903us 48 50 96.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.240s 3142.646us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 25.240s 3142.646us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 46.890s 2805.408us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 14.530s 2421.047us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 20.300s 2039.520us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 48 50 96.00
keymgr_lc_disable 5.370s 120.903us 48 50 96.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.300s 2039.520us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.300s 2039.520us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 20.300s 2039.520us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 17.800s 2189.402us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 20.300s 2039.520us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 50 54.00
keymgr_stress_all_with_rand_reset 28.730s 1303.282us 27 50 54.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 88573867569906356808142535575753769614303369768690130915185503971437275426727 364
UVM_ERROR @ 503592840 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 503592840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79663960814108823352553711159250112516030747825260415932430887351000836853167 104
UVM_ERROR @ 220550985 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 220550985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49336176692161799375890930976448116456112588902548197366988614305847632842147 282
UVM_ERROR @ 430099948 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 430099948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 25612531867557144350077713629315851444642979490243494412500680175046701904906 1234
UVM_ERROR @ 550526474 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 550526474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68562902812923575974705262734645136871948974575594212464179028599934021005028 575
UVM_ERROR @ 690884555 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 690884555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 69504326076577916612228130945468102479056683047589556254823653437739175626237 165
UVM_ERROR @ 902423636 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 902423636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103502835738817782485601699949854712516493385573968001047859646369099122758049 174
UVM_ERROR @ 104692928 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 104692928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 73860648724866672211192331247427837903420934653912793565532121108175191587486 543
UVM_ERROR @ 743582949 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 743582949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 109349004031484957067512397431386185778039959678013351891212293114407175827157 424
UVM_ERROR @ 326218736 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 326218736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46743248066501051810795281617200089845920218610232845837814091059284726325683 409
UVM_ERROR @ 555232174 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 555232174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 62092807405891993174200561554147288433416108326668464262848466972371404282205 1178
UVM_ERROR @ 2803890587 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2803890587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 60988725645006225498883281984314278166247442000076811263019127844762884662532 662
UVM_ERROR @ 198663627 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 198663627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 39400319941890726489759616995383777385500011327561651625433855311526331591682 525
UVM_ERROR @ 201450149 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 201450149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 47258171069795491680419688190597212662589609577240185641104266914582639541541 588
UVM_ERROR @ 719985654 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 719985654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 71031513477905772556873050347337268567735772566730014156271906073715100026289 202
UVM_ERROR @ 192470746 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 192470746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12789603419009013671725024583439009733926105226361764488674850303651729760333 139
UVM_ERROR @ 487245856 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 487245856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 41759467635571054076272727291797074677669146147704406065313564119331929254610 252
UVM_ERROR @ 111278655 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111278655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24181811827530294514917869730805904393185691625241313968308265494307246984796 444
UVM_ERROR @ 223521166 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 223521166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 8565857233298565756411512642359727900163387674146948556495275935976792046894 99
UVM_ERROR @ 440541635 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 440541635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 35461987901161292398997824891344757946065256129032469856687399038124722929142 986
UVM_ERROR @ 2774706372 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2774706372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98987069152367154569253650904172365905420255524962162821682767927509244676546 104
UVM_ERROR @ 167874415 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 167874415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 114770352590059075561329822346847979843014794976773555619319902804159050411541 836
UVM_ERROR @ 1562146789 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1562146789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103015617194331877315977493610105545768909266442927189662107526059250957987653 125
UVM_ERROR @ 125237522 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 125237522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 98615393441996948597093400708467564429324672984845440421579658867207360349634 789
UVM_ERROR @ 1656463469 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 1656463469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 105618093881628872985838097981730881670961222561400217062393090687713059884505 116
UVM_ERROR @ 38253219 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 38253219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 87409845514471430963802042896189160145213867228379487232467212466553171164338 2818
UVM_ERROR @ 6630507877 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6630507877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac
keymgr_lc_disable 76110758252174312590080420528738705656448679703596583174144275476471932113807 182
UVM_ERROR @ 32907834 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (840396466077365233209918294463135313325720854376106667080360472891884876334561959348829464320522896027006471610953990483899646158764679144037003929865340 [0x100bc5b94711f5d65aa47ed1c38d4786fd5f47f2940d350e8ee961987f0b10a934b94a569b0ae688dc76f2dda724b1837b67360c7506d2b5c1af0a21437c4c7c] vs 840396466077365233209918294463135313325720854376106667080360472891884876334561959348829464320522896027006471610953990483899646158764679144037003929865340 [0x100bc5b94711f5d65aa47ed1c38d4786fd5f47f2940d350e8ee961987f0b10a934b94a569b0ae688dc76f2dda724b1837b67360c7506d2b5c1af0a21437c4c7c]) KMAC key at state StCreatorRootKey for Attestation Kmac
UVM_INFO @ 32907834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes
keymgr_stress_all 13956372560891801341477247003355289733889276452575148594288009642440621340310 322
UVM_ERROR @ 709895680 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1319270146886176173566750580973597193536100308116951435887731816915692308331474764395582573953436736510225214990205046945093823788771686866132400030700885 [0x19307549731ea54cfa635b1abbefa75c114fd69bb9c3ee5baaf60f95457eb6ac6dd7fea946b80002e390ebea5226ec090593ddb915f16a10504aedd0e6215555] vs 1319270146886176173566750580973597193536100308116951435887731816915692308331474764395582573953436736510225214990205046945093823788771686866132400030700885 [0x19307549731ea54cfa635b1abbefa75c114fd69bb9c3ee5baaf60f95457eb6ac6dd7fea946b80002e390ebea5226ec090593ddb915f16a10504aedd0e6215555]) AES key at state StOwnerKey for Sealing Aes
UVM_INFO @ 709895680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---