Simulation Results: kmac

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.63 %
  • code
  • 94.21 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 80.28 %
Validation stages
V1
99.29%
V2
99.88%
V2S
99.19%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
kmac_smoke 87.340s 6818.544us 49 50 98.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.990s 65.928us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.200s 170.008us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.870s 1498.918us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.460s 489.990us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.110s 31.903us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.200s 170.008us 20 20 100.00
kmac_csr_aliasing 6.460s 489.990us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.870s 35.624us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.310s 33.595us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 49 50 98.00
kmac_long_msg_and_output 3482.850s 89652.896us 49 50 98.00
burst_write 50 50 100.00
kmac_burst_write 1337.340s 152428.997us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2117.170s 95513.061us 5 5 100.00
kmac_test_vectors_sha3_256 2097.070s 354084.902us 5 5 100.00
kmac_test_vectors_sha3_384 1747.690s 280852.418us 5 5 100.00
kmac_test_vectors_sha3_512 927.590s 62571.126us 5 5 100.00
kmac_test_vectors_shake_128 2455.220s 437011.798us 5 5 100.00
kmac_test_vectors_shake_256 2153.160s 89661.840us 5 5 100.00
kmac_test_vectors_kmac 3.710s 125.131us 5 5 100.00
kmac_test_vectors_kmac_xof 3.810s 127.360us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 502.970s 21136.123us 50 50 100.00
app 50 50 100.00
kmac_app 365.690s 22878.714us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 318.880s 34472.475us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 443.220s 214689.619us 50 50 100.00
error 50 50 100.00
kmac_error 480.380s 89858.075us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 20.660s 12471.923us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.290s 443.643us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 36.750s 538.528us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 34.800s 8695.139us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 70.940s 35498.656us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 29.650s 618.407us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2555.790s 147262.344us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.890s 24.370us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.300s 211.116us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.810s 260.338us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.810s 260.338us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.990s 65.928us 5 5 100.00
kmac_csr_rw 1.200s 170.008us 20 20 100.00
kmac_csr_aliasing 6.460s 489.990us 5 5 100.00
kmac_same_csr_outstanding 2.130s 407.918us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.990s 65.928us 5 5 100.00
kmac_csr_rw 1.200s 170.008us 20 20 100.00
kmac_csr_aliasing 6.460s 489.990us 5 5 100.00
kmac_same_csr_outstanding 2.130s 407.918us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.740s 326.056us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.740s 326.056us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.740s 326.056us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.740s 326.056us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 3.990s 2591.581us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.770s 1172.892us 20 20 100.00
kmac_sec_cm 122.860s 51065.374us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.770s 1172.892us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 29.650s 618.407us 50 50 100.00
sec_cm_sw_key_key_masking 49 50 98.00
kmac_smoke 87.340s 6818.544us 49 50 98.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 502.970s 21136.123us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.740s 326.056us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 122.860s 51065.374us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 122.860s 51065.374us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 122.860s 51065.374us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 49 50 98.00
kmac_smoke 87.340s 6818.544us 49 50 98.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 29.650s 618.407us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 122.860s 51065.374us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 348.160s 5882.581us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 49 50 98.00
kmac_smoke 87.340s 6818.544us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 205.420s 8205.281us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 81937746412170931375007148994631230680059751359889965104956666991725650485904 116
UVM_ERROR @ 20613879 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4122892755 [0xf5be59d3] vs 2430734887 [0x90e21227]) Regname: kmac_reg_block.prefix_2.prefix_0 reset value: 0x0
UVM_INFO @ 20613879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 89500126772802684811298961846601924335222845851703176013900819186650298457116 421
UVM_ERROR @ 3481351417 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3481351417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 32331289725878863697996840996607790809763076381410130893716912925362086470386 204
UVM_ERROR @ 3290077675 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3290077675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_long_msg_and_output 33384522868515351705911457803837993954226927460831191402864843877173376522131 74
UVM_ERROR @ 39839508 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 39839508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_smoke 112136547896671733569445127940618309521037316381787457763651888273591995420890 74
UVM_ERROR @ 51665576 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 51665576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---