Simulation Results: kmac

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.49 %
  • code
  • 92.34 %
  • assert
  • 97.74 %
  • func
  • 96.40 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.44 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.81%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 65.640s 3675.413us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.230s 108.616us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.150s 120.694us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.810s 2926.760us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.160s 1587.063us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.230s 140.216us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.150s 120.694us 20 20 100.00
kmac_csr_aliasing 7.160s 1587.063us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.010s 31.035us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.380s 148.706us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2856.630s 87897.974us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 871.270s 141574.321us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1893.170s 95567.973us 5 5 100.00
kmac_test_vectors_sha3_256 1849.900s 342866.221us 5 5 100.00
kmac_test_vectors_sha3_384 1316.620s 135176.163us 5 5 100.00
kmac_test_vectors_sha3_512 963.100s 247634.484us 5 5 100.00
kmac_test_vectors_shake_128 241.390s 59716.983us 5 5 100.00
kmac_test_vectors_shake_256 1240.160s 16765.659us 5 5 100.00
kmac_test_vectors_kmac 2.950s 112.770us 5 5 100.00
kmac_test_vectors_kmac_xof 3.420s 123.957us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 391.250s 19348.394us 50 50 100.00
app 50 50 100.00
kmac_app 317.290s 26251.958us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 347.280s 20461.266us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 319.290s 83754.736us 50 50 100.00
error 50 50 100.00
kmac_error 386.840s 80340.654us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 12.480s 5394.041us 50 50 100.00
sideload_invalid 40 50 80.00
kmac_sideload_invalid 173.950s 10059.936us 40 50 80.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.140s 21647.335us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.540s 1696.661us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 60.710s 27973.540us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 33.920s 1278.136us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2093.760s 191361.062us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.960s 71.415us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.200s 77.728us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.190s 407.160us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.190s 407.160us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.230s 108.616us 5 5 100.00
kmac_csr_rw 1.150s 120.694us 20 20 100.00
kmac_csr_aliasing 7.160s 1587.063us 5 5 100.00
kmac_same_csr_outstanding 2.140s 100.295us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.230s 108.616us 5 5 100.00
kmac_csr_rw 1.150s 120.694us 20 20 100.00
kmac_csr_aliasing 7.160s 1587.063us 5 5 100.00
kmac_same_csr_outstanding 2.140s 100.295us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.770s 72.247us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.770s 72.247us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.770s 72.247us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.770s 72.247us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.940s 908.103us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.810s 768.598us 20 20 100.00
kmac_sec_cm 64.380s 5699.849us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.810s 768.598us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 33.920s 1278.136us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 65.640s 3675.413us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 391.250s 19348.394us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.770s 72.247us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 64.380s 5699.849us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 64.380s 5699.849us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 64.380s 5699.849us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 65.640s 3675.413us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 33.920s 1278.136us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 64.380s 5699.849us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 230.310s 31241.528us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 65.640s 3675.413us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
kmac_stress_all_with_rand_reset 173.260s 4079.538us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 70185649493765944688819571908239802657170231480512138819738182315210653407333 277
UVM_ERROR @ 43644538214 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 43644538214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 96019453814089090160706764505951876489096665828929700808424485855142382013673 205
UVM_ERROR @ 1924337891 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1924337891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 46702922424210392763687817676099655829222932676548902507292785541807388370601 166
UVM_ERROR @ 30137900322 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30137900322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 24686514221341805072730331393127900719492982914507235817122465508399844085878 356
UVM_ERROR @ 34345375688 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 34345375688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 94199510730897452411790438140323855382258979745865004144150964962869499827499 205
UVM_ERROR @ 2398908124 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2398908124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 104470995895149826515332429001775054639330873259624623806817016799160247581214 78
UVM_FATAL @ 10609283419 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x33137000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10609283419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 5740114404760566787386937586032378589542358524368512244312109750334551996503 75
UVM_FATAL @ 10012458647 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9c321000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10012458647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 86013069964062662689003950267870524307506760040736339967755800173087053369212 75
UVM_FATAL @ 10014306108 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd1c96000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10014306108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 86433294577642961469496103728739898413585585514120794990482117331003283628748 85
UVM_FATAL @ 10059935572 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xaad97000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10059935572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 107305599043818115010195176521941417641686031062706245937427803952436308865804 81
UVM_FATAL @ 10199045238 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x43fef000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10199045238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 48195747251766911291155955599558200929855224357145579628165795228912737746509 82
UVM_FATAL @ 10035952600 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x36446000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10035952600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 48755616384833606062517571880138607264138866841862761431339777894034067453779 76
UVM_FATAL @ 10041708860 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x269de000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10041708860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23)
kmac_sideload_invalid 70909615892075471578133035539519374195466704590686185110857854930678478751536 101
UVM_FATAL @ 10402205230 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdf85c000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
UVM_INFO @ 10402205230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 108774102645020106532096811634515267031970014753308794687383371082996145892956 77
UVM_FATAL @ 10069660792 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x911a4000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10069660792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 2331768269374452519982277610627287877669650695409298944626614092109916915865 91
UVM_FATAL @ 10325362838 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x24e8c000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10325362838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---