Simulation Results: otbn

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.22 %
  • code
  • 95.84 %
  • assert
  • 89.83 %
  • func
  • 100.00 %
  • block
  • 99.59 %
  • line
  • 99.66 %
  • branch
  • 95.20 %
  • toggle
  • 93.64 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
99.13%
V2S
98.03%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 8.000s 37.974us 1 1 100.00
single_binary 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 9.000s 26.695us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 9.000s 24.869us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 11.000s 834.043us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 17.773us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 14.000s 43.654us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 9.000s 24.869us 20 20 100.00
otbn_csr_aliasing 8.000s 17.773us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 57.000s 3581.681us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 20.000s 2180.948us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 40.000s 346.911us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 50.000s 355.875us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 113.000s 470.723us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 91.000s 247.527us 9 10 90.00
lc_escalation 58 60 96.67
otbn_escalate 43.000s 174.685us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 29.202us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 17.000s 50.653us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 14.000s 19.910us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 8.000s 31.384us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 12.000s 251.404us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 12.000s 251.404us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 9.000s 26.695us 5 5 100.00
otbn_csr_rw 9.000s 24.869us 20 20 100.00
otbn_csr_aliasing 8.000s 17.773us 5 5 100.00
otbn_same_csr_outstanding 12.000s 50.504us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 9.000s 26.695us 5 5 100.00
otbn_csr_rw 9.000s 24.869us 20 20 100.00
otbn_csr_aliasing 8.000s 17.773us 5 5 100.00
otbn_same_csr_outstanding 12.000s 50.504us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 11.000s 22.789us 10 10 100.00
otbn_dmem_err 15.000s 46.444us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 12.000s 33.074us 5 5 100.00
otbn_controller_ispr_rdata_err 40.000s 277.819us 5 5 100.00
otbn_mac_bignum_acc_err 44.000s 154.254us 5 5 100.00
otbn_urnd_err 8.000s 21.106us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 28.589us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 24.467us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 10.000s 34.890us 9 10 90.00
tl_intg_err 24 25 96.00
otbn_tl_intg_err 27.000s 362.283us 20 20 100.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
passthru_mem_tl_intg_err 15 20 75.00
otbn_passthru_mem_tl_intg_err 30.000s 240.996us 15 20 75.00
prim_fsm_check 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
prim_count_check 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 8.000s 37.974us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 15.000s 46.444us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 11.000s 22.789us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 27.000s 362.283us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 43.000s 174.685us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 22.789us 10 10 100.00
otbn_dmem_err 15.000s 46.444us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 29.202us 5 5 100.00
otbn_illegal_mem_acc 7.000s 28.589us 5 5 100.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_controller_fsm_sparse 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 22.789us 10 10 100.00
otbn_dmem_err 15.000s 46.444us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 29.202us 5 5 100.00
otbn_illegal_mem_acc 7.000s 28.589us 5 5 100.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_scramble_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 43.000s 174.685us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 22.789us 10 10 100.00
otbn_dmem_err 15.000s 46.444us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 29.202us 5 5 100.00
otbn_illegal_mem_acc 7.000s 28.589us 5 5 100.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 16.000s 69.758us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 18.000s 64.677us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 62.000s 555.241us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 62.000s 555.241us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 17.000s 66.909us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_stack_wr_ptr_ctr_redun 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 14.000s 74.617us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_loop_stack_ctr_redun 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 22.000s 65.394us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 22.000s 65.394us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 6 7 85.71
otbn_sec_wipe_err 16.000s 45.350us 6 7 85.71
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 113.000s 470.723us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 16.000s 239.029us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 23.000s 341.516us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 4 5 80.00
otbn_sec_cm 1462.000s 6287.583us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
otbn_stress_all_with_rand_reset 569.000s 10459.607us 5 10 50.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 26141703119082325323446236632212883632965638985133932363105557033853398402625 88
UVM_FATAL @ 101036420 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 101036420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 79261649765216332421798695183727784122573716842257248585524492743467321849432 83
UVM_FATAL @ 4098905 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 4098905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 25270628186550963747689296882377546851403326818090725984946710216819231571153 93
UVM_FATAL @ 77551240 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 77551240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 64300672327028687549872158206345842004341785133346838958944118905615024672094 83
UVM_FATAL @ 2252242 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 2252242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 87903578677421998065449667758533550193772404866503669497859615465888207966442 83
UVM_FATAL @ 3103034 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 3103034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
otbn_stress_all 27242077801149228996533021239964999511386942289123721197082979585944458056165 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 27242077801149228996533021239964999511386942289123721197082979585944458056165 --size 2000 --count 10 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest run_opts='+test_timeout_ns=10000000000 +otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=244011493 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_stress_all.244011493 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_stress_all.244011493 -covoverwrite' seed=27242077801149228996533021239964999511386942289123721197082979585944458056165 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_stress_all_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 27242077801149228996533021239964999511386942289123721197082979585944458056165 --size 2000 --count 10 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all/latest
2025/12/14 13:04:29 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 59932233665423652974425019350388303281302832835515416576834027641623627990845 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 45350454 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 45350454 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 45350454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 103170409834440295660057954446240851101635339844748059421663746184825270968874 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19857207 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 19857207 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19857207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
otbn_rf_base_intg_err 75765140225578340571457372730425432239074910530338468206168656371048296637498 114
UVM_ERROR @ 10942027 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 10942027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 12994900430162457834046607669267728390342609726014352239646685710727123127042 203
UVM_ERROR @ 1153527107 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1153527107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 33956933574542180508846080738326790615601961961451006373454575633322368891699 100
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 50131321 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 50131321 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 50131321 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 50131321 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 50131321 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 55916644003753689281676572819612168212042933897691076010457323977132429617144 109
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3460780 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 3460780 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3460780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 80436996562323949968283432276339039626048669561919170494318224307856109974765 338
UVM_FATAL @ 1010168996 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1010168996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 109032520432037635534831087894008149074452723903547857196884077585498425147137 517
UVM_FATAL @ 3140733054 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 3140733054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 115279270109904571761284037753372623390984883742070061125917326858393216484314 289
UVM_ERROR @ 10459607065 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10459607065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90990813012416984273866684246318434548444403704746626379281427803856300173281 212
UVM_ERROR @ 1365345729 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1365345729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 48972227093250076545490605379558537376690258259375813085578432850091589256080 111
UVM_ERROR @ 1829587 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1829587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---