Simulation Results: otp_ctrl

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.82 %
  • code
  • 85.43 %
  • assert
  • 94.63 %
  • func
  • 92.39 %
  • line
  • 89.74 %
  • branch
  • 85.71 %
  • cond
  • 91.80 %
  • toggle
  • 95.83 %
  • FSM
  • 64.06 %
Validation stages
V1
97.16%
V2
91.59%
V2S
95.26%
V3
0.99%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.870s 814.850us 1 1 100.00
smoke 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
csr_hw_reset 5 5 100.00
otp_ctrl_csr_hw_reset 2.760s 82.078us 5 5 100.00
csr_rw 20 20 100.00
otp_ctrl_csr_rw 3.290s 597.589us 20 20 100.00
csr_bit_bash 5 5 100.00
otp_ctrl_csr_bit_bash 12.540s 1718.457us 5 5 100.00
csr_aliasing 5 5 100.00
otp_ctrl_csr_aliasing 12.500s 3313.481us 5 5 100.00
csr_mem_rw_with_rand_reset 16 20 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.410s 287.891us 16 20 80.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otp_ctrl_csr_rw 3.290s 597.589us 20 20 100.00
otp_ctrl_csr_aliasing 12.500s 3313.481us 5 5 100.00
mem_walk 5 5 100.00
otp_ctrl_mem_walk 1.940s 144.739us 5 5 100.00
mem_partial_access 5 5 100.00
otp_ctrl_mem_partial_access 1.760s 73.162us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 20.910s 12634.703us 1 1 100.00
init_fail 279 300 93.00
otp_ctrl_init_fail 7.160s 2254.476us 279 300 93.00
partition_check 21 60 35.00
otp_ctrl_background_chks 37.420s 3324.384us 6 10 60.00
otp_ctrl_check_fail 22.340s 2996.049us 15 50 30.00
regwen_during_otp_init 50 50 100.00
otp_ctrl_regwen 12.740s 3606.317us 50 50 100.00
partition_lock 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
interface_key_check 50 50 100.00
otp_ctrl_parallel_key_req 44.130s 22281.496us 50 50 100.00
lc_interactions 250 250 100.00
otp_ctrl_parallel_lc_req 41.850s 11644.602us 50 50 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_dai_errors 49 50 98.00
otp_ctrl_dai_errs 51.560s 14527.205us 49 50 98.00
otp_macro_errors 18 50 36.00
otp_ctrl_macro_errs 41.630s 22977.718us 18 50 36.00
test_access 50 50 100.00
otp_ctrl_test_access 36.830s 6474.350us 50 50 100.00
stress_all 42 50 84.00
otp_ctrl_stress_all 265.060s 177342.847us 42 50 84.00
intr_test 50 50 100.00
otp_ctrl_intr_test 2.930s 530.031us 50 50 100.00
alert_test 50 50 100.00
otp_ctrl_alert_test 3.630s 208.468us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otp_ctrl_tl_errors 6.440s 355.848us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otp_ctrl_tl_errors 6.440s 355.848us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otp_ctrl_csr_hw_reset 2.760s 82.078us 5 5 100.00
otp_ctrl_csr_rw 3.290s 597.589us 20 20 100.00
otp_ctrl_csr_aliasing 12.500s 3313.481us 5 5 100.00
otp_ctrl_same_csr_outstanding 7.280s 2244.757us 20 20 100.00
tl_d_partial_access 50 50 100.00
otp_ctrl_csr_hw_reset 2.760s 82.078us 5 5 100.00
otp_ctrl_csr_rw 3.290s 597.589us 20 20 100.00
otp_ctrl_csr_aliasing 12.500s 3313.481us 5 5 100.00
otp_ctrl_same_csr_outstanding 7.280s 2244.757us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
tl_intg_err 24 25 96.00
otp_ctrl_tl_intg_err 23.420s 4809.718us 20 20 100.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
prim_count_check 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
prim_fsm_check 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_bus_integrity 20 20 100.00
otp_ctrl_tl_intg_err 23.420s 4809.718us 20 20 100.00
sec_cm_secret_mem_scramble 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_part_mem_digest 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_dai_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_kdi_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_lci_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_part_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_scrmbl_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_timer_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_dai_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_kdi_seed_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_kdi_entropy_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_lci_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_part_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_scrmbl_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_timer_integ_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_timer_cnsty_ctr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_timer_lfsr_redun 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_part_fsm_local_esc 218 250 87.20
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_macro_errs 41.630s 22977.718us 18 50 36.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_part_fsm_global_esc 218 250 87.20
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_macro_errs 41.630s 22977.718us 18 50 36.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 40.460s 15412.412us 200 200 100.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_part_data_reg_integrity 279 300 93.00
otp_ctrl_init_fail 7.160s 2254.476us 279 300 93.00
sec_cm_part_data_reg_bkgn_chk 15 50 30.00
otp_ctrl_check_fail 22.340s 2996.049us 15 50 30.00
sec_cm_part_mem_regren 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_part_mem_sw_unreadable 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_part_mem_sw_unwritable 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_lc_part_mem_sw_noaccess 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_access_ctrl_mubi 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
otp_ctrl_dai_lock 43.690s 20033.737us 50 50 100.00
sec_cm_test_bus_lc_gated 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 4 5 80.00
otp_ctrl_sec_cm 163.400s 21262.398us 4 5 80.00
sec_cm_direct_access_config_regwen 50 50 100.00
otp_ctrl_regwen 12.740s 3606.317us 50 50 100.00
sec_cm_check_trigger_config_regwen 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_check_config_regwen 50 50 100.00
otp_ctrl_smoke 10.830s 1898.177us 50 50 100.00
sec_cm_macro_mem_integrity 18 50 36.00
otp_ctrl_macro_errs 41.630s 22977.718us 18 50 36.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.940s 3045.859us 1 1 100.00
stress_all_with_rand_reset 0 100 0.00
otp_ctrl_stress_all_with_rand_reset 34.130s 16388.756us 0 100 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 4418074483953534726058384834644705672544092642121918770196998193735356803761 89
UVM_ERROR @ 107593515 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107593515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 13490136125073827082193194987791419987652549900360677509721082833203840873 89
UVM_ERROR @ 429013516 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 429013516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 110274793978586022225632182883946000288324535183963635923715059447535563834533 89
UVM_ERROR @ 107405944 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107405944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 67180536614702345791395126880856774926425472214554992355458782545115027657429 95
UVM_ERROR @ 125887427 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 125887427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76536750541184335097237096227198628944574193466922273574216453603169134056923 90
UVM_ERROR @ 108324316 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 108324316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61796436797765131896555738594648203444043228465766671158486880885302166805151 112
UVM_ERROR @ 459361408 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 459361408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4188108725862254015307822628812594016331079857036202975457861602411264867644 89
UVM_ERROR @ 432044351 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 432044351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72740986853582418195394727483460735764277706544063697060103825255006375469004 191
UVM_ERROR @ 2810556170 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 2810556170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37405499173420495083622588362463993027893529930388344251562452976192514492825 90
UVM_ERROR @ 54444267 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54444267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62579332747099949111934961085213535555404965691153100196231831722641508361843 92
UVM_ERROR @ 27696254 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27696254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10830791555540976668314517211223219757389244533369906457983759062577347072093 96
UVM_ERROR @ 26402031 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26402031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95348345304741062420742635568825776466691661130606504044996268417896192407015 89
UVM_ERROR @ 26337997 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26337997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68968758343392274925569448767125074177494795502516830614825335012724087322422 90
UVM_ERROR @ 27306708 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27306708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23332014491586753137215430633315069531883804138149018601953692407828952176831 96
UVM_ERROR @ 113508130 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 113508130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93156787662532467592211950477781861825082656044430973800470523760752848083278 97
UVM_ERROR @ 106742063 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 106742063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42149474304584625293849535453754153873065686223141676507860364014971542139060 92
UVM_ERROR @ 47425894 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 47425894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22979244610446322204688647951019822824122301142494707898653714416673789908989 10823
UVM_ERROR @ 869861395 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 869861395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52963232698997170376479154727476368875225535183112440251832384788994793283668 15308
UVM_ERROR @ 436145019 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 436145019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65669053889079685906569134457064199462783115656267952808415023208441061643935 90
UVM_ERROR @ 26291106 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26291106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74493077296831025649735056507748609881242545053315042572233963401051032402175 92
UVM_ERROR @ 25826493 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 25826493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20566263182837625135300430777280623367416251186882089249309667560513317024362 89
UVM_ERROR @ 67918391 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 67918391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105632779625138641283467243884709778036755245305716464074770396873762547216536 96
UVM_ERROR @ 53176098 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53176098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23263854770389075345348772206275336651532418710859563157373057868660862977921 92
UVM_ERROR @ 26529707 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26529707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19194933030840602493105342709466013219974758679245782853053132902593108661619 96
UVM_ERROR @ 448592096 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 448592096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50152530804752438056918469284413903211497270544648430373334413084912486322082 100
UVM_ERROR @ 104786425 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104786425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57214036167538654189762876919351761285353785780303968279361321124055241024551 92
UVM_ERROR @ 28138193 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28138193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90956052117809822476236714274244224487685610559396441928774932425881231757735 90
UVM_ERROR @ 52098969 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52098969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102703305738776115672949502044888764750162348016730218282618570470947764053112 96
UVM_ERROR @ 56865548 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56865548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34120991663984014510803558173773909239368647140861686752000214658443452932491 99
UVM_ERROR @ 28261619 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 28261619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7046123180794208820755336227348908306314209656486763083439146934680812567058 432
UVM_ERROR @ 1141583060 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1141583060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65382532111393839630681209653215804684268877523675162731226296670869432715363 91
UVM_ERROR @ 52667692 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52667692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37711166237344906873800805476611504698988917153959926048798284566135474013570 3740
UVM_ERROR @ 9099147192 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 9099147192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76464439146429527671318240384304353556768916432126634137966447943580306574967 102
UVM_ERROR @ 82265933 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 82265933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70264129599926562268501107489822192572482544938900818264866137690068034482245 90
UVM_ERROR @ 108898756 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 108898756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13201390201831436300907818194783296207499665114741221619239195584542901833178 94
UVM_ERROR @ 431934794 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431934794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114339274065432903365213262170479093408388833558611784829174206466983187243069 2460
UVM_ERROR @ 1826245523 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1826245523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9694159093588280826030068426484404172657888349238514401374667915957947125998 89
UVM_ERROR @ 431679629 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431679629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8662443109696431270134267534930120471351706925112721361168946466481297141097 90
UVM_ERROR @ 53149999 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53149999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115249699152716053562990794095893891647260873911214969488091183170064152813177 90
UVM_ERROR @ 39567033 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 39567033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41096422488736725350835664219171035061419097798411816434306492959034872126755 96
UVM_ERROR @ 432985287 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 432985287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63227990897738611988802168304387710728898388069099411293248814046207586281604 89
UVM_ERROR @ 32441760 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 32441760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80500968442449358524301957657608767897013079562943639257476802570498359249328 92
UVM_ERROR @ 430076978 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 430076978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38424934639825661675853531833648247191487137676125206253557260301786468075204 89
UVM_ERROR @ 48584913 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 48584913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48335289666990718610852790417562651079204378604244714999956909515399892656315 89
UVM_ERROR @ 106170358 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 106170358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24377242831384393888555869920231992494663470282994020247769512882375674465956 94
UVM_ERROR @ 26621207 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 26621207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37929459056318522814788525738619023868119744484879985772705797169889442391950 7002
UVM_ERROR @ 16388756041 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 16388756041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114383914180323630086620470383163749090447345802071908327919734915417087766905 477
UVM_ERROR @ 291361085 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 291361085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18146141392078301614164430286563335863304075197448211896468645205312653392453 92
UVM_ERROR @ 434264835 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 434264835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41967658090829855452863880844518468066334878687470365808444986414554000681283 89
UVM_ERROR @ 43931807 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 43931807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33867770673142265331254533815991090765745205615449650164594447413944807386631 89
UVM_ERROR @ 49250649 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 49250649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45334231114963721776714878492517763799010740785921329619094191230779125339661 92
UVM_ERROR @ 62999750 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 62999750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63374240279075445508489181223378204389917771287540900446827733192893431920378 89
UVM_ERROR @ 29016652 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29016652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23370209904392192585883220000218123553816876766265211550024988441308449088481 96
UVM_ERROR @ 81772159 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 81772159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101939855287870723148427754014924302268534749443772349194388903645652525439816 96
UVM_ERROR @ 45711953 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 45711953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82189631260525792323073090106497490441216544812743286495944385795818112568584 92
UVM_ERROR @ 53721183 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53721183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29538716574234207300754256307859530186540649139782318416439037539575654673646 91
UVM_ERROR @ 60516220 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 60516220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20776390181296232667198895349007123260646464238229419965580439313016972693739 90
UVM_ERROR @ 80905950 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 80905950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33886230958671967953211728295740105774164936221447878780916587542028305603707 98
UVM_ERROR @ 27439523 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27439523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88822740570009597493349334989896797618039209085331907158325319802387650539445 94
UVM_ERROR @ 47415235 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 47415235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105560740786320777591558378085689242384447066728312853062862339652756750762772 98
UVM_ERROR @ 49195946 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 49195946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96975956022995521236886633477046958701514497043266515007954241647800661063520 92
UVM_ERROR @ 67230610 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 67230610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1764991256642152817749599604910734563967686688128080049893334473780726427611 90
UVM_ERROR @ 428661703 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 428661703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105895737985218030982534152993216217980038354887332980962983793306867375305282 186
UVM_ERROR @ 999315332 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 999315332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21118354560471993764369261284962335452676529621533533308636567279886123251367 194
UVM_ERROR @ 15047910546 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 15047910546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106590283146459137824019263315241255377251082914950928219134476213114990468813 89
UVM_ERROR @ 138849599 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 138849599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106990296162869960113915934003778556745476993357766605610240844566924382730160 92
UVM_ERROR @ 111301851 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 111301851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30446243568353078797993000001483143898516694994099172963383278371046823103102 7517
UVM_ERROR @ 268693557 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 268693557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37959034029674407315455025201432225413823346443242756581456889806645557430796 96
UVM_ERROR @ 446040906 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 446040906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42904802696397817288250333050010697839253873489901840040338287222568149235644 1007
UVM_ERROR @ 259650188 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 259650188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17299413900414560811182548625142133259261252477805000179749152842505744859256 100
UVM_ERROR @ 56694570 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56694570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5799645772236866970660461674852779134615661572135307534700220945665961494690 90
UVM_ERROR @ 432816532 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 432816532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31397136580800142752152589536972849840721292195737373197525427198862142892947 92
UVM_ERROR @ 103122802 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 103122802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53167003217751492316021778742057992822479772148470128392752121563572330109586 94
UVM_ERROR @ 107962221 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107962221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105001742691086296932313540080512058639903930094529414693114956958005791051848 89
UVM_ERROR @ 27018401 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27018401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 929971539376370661319471760417853868951021104465391371210522330566011156593 89
UVM_ERROR @ 55261756 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 55261756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31164175808272525920535060429231619813880862287748809657233695514849165467103 90
UVM_ERROR @ 107247207 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107247207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15018341156481963305780857291189718939155853870545057429768632831614585018550 89
UVM_ERROR @ 104015415 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 104015415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66940213700602064479698334971048307064937973077246547119199333282449389189812 90
UVM_ERROR @ 52115787 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 52115787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29246101236417160163181743963147853304098939892991800156948910401837159390100 89
UVM_ERROR @ 56453609 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 56453609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3743410565201751534455798401540280737350030355895348663329874998464696716101 3436
UVM_ERROR @ 6721535758 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 6721535758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53804323576047313956877854019999209751477256092619645636651634508105115431518 92
UVM_ERROR @ 29689038 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 29689038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12868246996190743687886359847829149224505497284174049090851015148045821104893 90
UVM_ERROR @ 434328319 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 434328319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88362582128201052069680326916213412867584555523886589984496866952963341458480 90
UVM_ERROR @ 431573980 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 431573980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54214952514546830942732133205786023909176230002391751177423638684400849060491 94
UVM_ERROR @ 445738350 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 445738350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25691390981316672413201705971681140754716618228057534202764487493631246800434 96
UVM_ERROR @ 449529800 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 449529800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14414150266698953426438301467626755712227218251625548804638594480224573720265 91
UVM_ERROR @ 25917405 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 25917405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59364072055597051438641788839057830019212910655266816523038144055007998523639 217
UVM_ERROR @ 61207072 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 61207072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21178738912612808054700700234112386804991128534684091706064139564018167291246 110
UVM_ERROR @ 73791902 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 73791902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77465742476907753508391237970389852201278303337881949325365623644375390196639 9150
UVM_ERROR @ 1163312639 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1163312639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 3507197761169692474704077832868878178685982907076503986986132370158645802505 92
UVM_ERROR @ 105297573 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 105297573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96057416992402431796897330261846302253343053800464711582445424917281761891923 222
UVM_ERROR @ 3408325320 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 3408325320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95677971480888456446216727814892550971740173353161172935465210789953507854615 3891
UVM_ERROR @ 898043868 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 898043868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100114508582932093339368706934109411291482899935047454456689297769447419647551 92
UVM_ERROR @ 45510622 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 45510622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53763479367450431423559270562882634370476154824272596916111568572327554750800 429
UVM_ERROR @ 436478458 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 436478458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57881148310438257947569892880717723400452494006810318988718601471468861908919 94
UVM_ERROR @ 27482889 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27482889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114509221033082591670473844943371731646898480810637466578731629255755627091687 89
UVM_ERROR @ 434797929 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 434797929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56517824071790329249090991697605000198077529173829364056186615367015447596871 106
UVM_ERROR @ 73086810 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 73086810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64239094095056989216641115209589253169809716502017853227254070870222872601953 90
UVM_ERROR @ 102873821 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 102873821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107528698076524826404571367336510264955377093589329663725340787872311328287655 89
UVM_ERROR @ 53554083 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53554083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4996898185084693010390008546028821793892303633346222670783148230479563917984 92
UVM_ERROR @ 27231433 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 27231433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19105425040431386602165497420264030267599384054326063863063309214995338243003 90
UVM_ERROR @ 107731618 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 107731618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51158752996947606790605445122885810009812614106681548349566806790270642424530 111
UVM_ERROR @ 53491804 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53491804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67359703944715178888103618763689216899227912288874664066173571408464233345796 219
UVM_ERROR @ 1332059297 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1332059297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22799835923152115689128483222276653837873607123901466811892972456706177871021 92
UVM_ERROR @ 53287591 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 53287591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 86467991989155479132865898040685262618742414330834798221117048183370364736039 10839
UVM_ERROR @ 6435109235 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6435109235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 36040196922533601010559769608661606107442058241400343610445007319845862150716 21056
UVM_ERROR @ 772102187 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 772102187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 85630361817411463842559328498678844221252994137088226149491601338682173772051 34220
UVM_ERROR @ 25975919541 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 25975919541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 4974183314855258966831156152102384589063295184098333555407342381973788199506 16973
UVM_ERROR @ 3324383566 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 3324383566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 85460067514271042826567805061684814364699853346998056667807259693485239418488 15066
UVM_ERROR @ 6070229651 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 6070229651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 72423440006742308254615547919780774209850583883707591932333208165031107960449 3076
UVM_ERROR @ 2112347960 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2112347960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 80852339803023630895621783704358536739330167142477797731385377844625181026672 36763
UVM_ERROR @ 39195102044 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 39195102044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 56889312488856704558363457688924500653529914501188803102924042805357414631292 49049
UVM_ERROR @ 1921774870 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1921774870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 63628672730879981041910854936450990186156120165249953744382114625442271037519 59557
UVM_ERROR @ 19193267579 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 19193267579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 34355585164324898769044322380424903668861079677276025066746078833770467916870 12306
UVM_ERROR @ 24967297994 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 24967297994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 29983975458589365983688904958167593819375707874105516506663310100547598078400 74714
UVM_ERROR @ 5398507526 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 5398507526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 66213345577045868540362177083395079706287994177124863965011739730781916218603 9616
UVM_ERROR @ 4571498648 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3020351992 [0xb406e9f8] vs 3020343800 [0xb406c9f8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4571498648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 40328667997378187664385389997140590165124498199175526881176656787376450325049 916
UVM_ERROR @ 51847796 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4004988952 [0xeeb74818] vs 4004988953 [0xeeb74819]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 51847796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 101741407235541529239548221680055947428145926883564476650144629907289998776599 128
UVM_ERROR @ 91460913 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 91460913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 913702706578701142549061972317351725324531067085052258311082880467252811149 3727
UVM_ERROR @ 170299159 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1573427888 [0x5dc89ab0] vs 1573444272 [0x5dc8dab0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 170299159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 7301219549221721036483182456861974439858182742583391542205840495748098736348 3747
UVM_ERROR @ 2237451500 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 33 [0x21]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2237451500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68500663296749241446385008868848153147304687360288813132556269660372511816680 8437
UVM_ERROR @ 581224083 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 581224083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73573002805058700003224454281895124722722484055849364841171085274330930640300 3787
UVM_ERROR @ 4886469220 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4190466362 [0xf9c5713a] vs 4190466490 [0xf9c571ba]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4886469220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32939663509714200844386495207152139765164306873402821825633736379031073269362 8366
UVM_ERROR @ 308329868 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1344889166 [0x5029614e] vs 1344921934 [0x5029e14e]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 308329868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 115015692661356486544076752533267993240852232158910822099810205029983200997385 108
UVM_ERROR @ 510576324 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 510576324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 63146042821079144302663277305498595798026282983504252916327609705280667840976 190
UVM_ERROR @ 57155968 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 36864 [0x9000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 57155968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31381724644003160092763793905299158387592964183458531448544126480254039818984 14640
UVM_ERROR @ 2091054224 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2091054224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 94806390882159617764249318923857252274558145103781772534379526047337024785400 1924
UVM_ERROR @ 53048561 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 64 [0x40]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 53048561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 53016644332107622500647958543721126592151043177803718954733991080757325234798 12056
UVM_ERROR @ 2914825358 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2048 [0x800]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2914825358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 47919071785676666971131578064197091309409208710209364049016901389317881941112 160
UVM_ERROR @ 55215871 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3603903555 [0xd6cf3443] vs 3603903554 [0xd6cf3442]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 55215871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54715123126170733112096573546458626413321040595251825648520306757421239077372 1698
UVM_ERROR @ 268822120 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 268822120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 2369149029412820310427036301431661088897775131145720052993856448255634966144 1297
UVM_ERROR @ 224174911 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1920510008 [0x7278a838] vs 1920510072 [0x7278a878]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 224174911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95877886582264498041649801095563374067097018345515656469664140987855402956700 3068
UVM_ERROR @ 1108837024 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1108837024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 50500797503184865362147538124257750797598641965329180214294211831620198195100 1245
UVM_ERROR @ 254324147 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 254324147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76740786165803924543279653760599380528876929194969999205335742890729212062972 228
UVM_ERROR @ 62712844 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 62712844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64767279076799079396466281039529101204685399832521719957732273221417921451292 11716
UVM_ERROR @ 1506078587 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1084203406 [0x409fa18e] vs 1084195214 [0x409f818e]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1506078587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 63891096311468241159669461432692144877882925322645789217137590291058309237550 3214
UVM_ERROR @ 318209547 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (443210300 [0x1a6ada3c] vs 2071977981 [0x7b7fdffd]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 318209547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 11985913179814819323596545461254464938555840711523068555057851409100621305957 6166
UVM_ERROR @ 2996049369 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514892422 [0x95e63686]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2996049369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84510150962588680165133798849379735014667415510148694863428727101854021507712 6368
UVM_ERROR @ 3122052908 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1590163168 [0x5ec7f6e0] vs 1590163169 [0x5ec7f6e1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3122052908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 28988843346636840946776045797433718799166253121979230811806453371119535305841 2518
UVM_ERROR @ 91886750 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 91886750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 110348212579922246325555661590142070214082240546530475078578208437660852540220 1642
UVM_ERROR @ 78184039 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4128 [0x1020]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 78184039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 2480408529011931405723216778232581974510697419170147740116594128923891318773 842
UVM_ERROR @ 129138541 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 129138541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 55085784715305504113027313234564149890322045022182695578371362538308074731778 2180
UVM_ERROR @ 504734751 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1977769616 [0x75e25e90] vs 1977767568 [0x75e25690]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 504734751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 65958680343439517827413308692372897575889361841328688511409828716657774634055 2048
UVM_ERROR @ 186048863 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 186048863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 49958144629570787448801914064004403938548340477025598120124975681774537159991 1166
UVM_ERROR @ 100484319 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2520721960 [0x963f2a28] vs 2520722216 [0x963f2b28]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 100484319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54649749676301534677987037253795248295701490856810292511416841840693970206636 11793
UVM_ERROR @ 1210647234 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1210647234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 87874501352956178680647691802815453723537167242881222394181130082885389191118 1970
UVM_ERROR @ 50964528 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 50964528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95869692182928896757082323361316734614927746834476311617053357176235349998110 818
UVM_ERROR @ 1410166191 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1410166191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 15711739005707338780739370936357330820549419512567339729471735288872570020755 25203
UVM_ERROR @ 4682012747 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4189190137 [0xf9b1f7f9]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 4682012747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 66026594124537661828536992248084475140474967724352187588768303544200087316059 226
UVM_ERROR @ 548896858 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (300065745 [0x11e2a3d1] vs 300065425 [0x11e2a291]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 548896858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29198560253495930609172353184869820955954289422292827538127882396915599748781 6668
UVM_ERROR @ 1399586816 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1399586816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31858531919664861815715532637960090417248900371085356632900951906393349777806 12082
UVM_ERROR @ 507270302 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 20 [0x14]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 507270302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 83807958224071672763238283382057464679778655449781595762211896975536531724719 1976
UVM_ERROR @ 148255803 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 148255803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 81831498537485596097365463038278476635316952768319388953989285348416692800627 4032
UVM_ERROR @ 451887495 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1451531305 [0x56849c29] vs 1451527209 [0x56848c29]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 451887495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73189630347380592486081502476852528780950017886133288008068559641518642412344 1016
UVM_ERROR @ 1298379649 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1173783536 [0x45f683f0] vs 1173783540 [0x45f683f4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 1298379649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 102661205408057167816759871497385122775181653549764593721241864995868990052740 2648
UVM_ERROR @ 352645713 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 352645713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 86524159734818006762194513821176355735360309097844021741647954691847246999130 5576
UVM_ERROR @ 819500639 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (466750112 [0x1bd20aa0] vs 466749984 [0x1bd20a20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 819500639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 81651002462011980596361878375281282734512556447981103070315692927115334800632 150
UVM_ERROR @ 39254020 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16 [0x10]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 39254020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 65906245132780791769239122938993603471458783731863682976310411375119633083521 462
UVM_ERROR @ 34107387 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 34107387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 1689549857146334308401945815239744664825997064070448459427176046076020078479 346
UVM_ERROR @ 179329524 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2338935406 [0x8b69526e] vs 2338968174 [0x8b69d26e]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 179329524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 93877847578736445212165856222666352916010361428140117082303770505900701559149 1337
UVM_ERROR @ 332552515 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32770 [0x8002]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 332552515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 13863155751155394886542722636310217088042367058003692543659472913570991570068 8900
UVM_ERROR @ 261415581 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 261415581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49417255772112125336662122248526069213512940475535890505363910559549047247908 4408
UVM_ERROR @ 3434332477 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3434332477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 15545838950509878321291339951234075111614485764722645231921460683327668539444 470
UVM_ERROR @ 65817454 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 65817454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35163773021028405416017135761662478056404968615626039123705303509974866257022 1224
UVM_ERROR @ 273750143 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 273750143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 77322267822979586312586762287075866120984735688876507022226638686808260831770 4289
UVM_ERROR @ 220595886 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 220595886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 69796027974872955173936479273526512653875166777592552130207576691799507788650 8098
UVM_ERROR @ 12207491766 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514925186 [0x95e6b682]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 12207491766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17998751513713374517904337873230563915973002900287391542627392291898340488511 4491
UVM_ERROR @ 7086421083 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2514892418 [0x95e63682] vs 2514892416 [0x95e63680]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 7086421083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 110123668894287422304471764181133084988528712730109043287530258830016698594104 1309
UVM_ERROR @ 2364203344 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2 [0x2]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 2364203344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 89013480731649107257579335517744467711778168883042693857029301264020047656428 6946
UVM_ERROR @ 548922571 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 548922571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 46599992854191742288458449181680988940527211115967800844382883943987464621402 920
UVM_ERROR @ 71554175 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 71554175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104386745723734048411437537795707104462634524153793837284279731621882433187255 2157
UVM_ERROR @ 3575160348 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 128 [0x80]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 3575160348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 106524008442161686824023390912141618772403591863412667513383259674860224523491 16782
UVM_ERROR @ 841224636 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 256 [0x100]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 841224636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:691) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_check_fail 103848260244921169479972065962025908158710024702289367825893581953587795225677 2498
UVM_ERROR @ 357601605 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 357601605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 5676150840003754285014483570320898284033512095219114931928367506665781416739 1746
UVM_ERROR @ 258882080 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 258882080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 100764534486963024513452132286467550159654364892594847190617921811265567735885 5604
UVM_ERROR @ 506894736 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 506894736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 95408898872289091038925270914684745189858568844199670092716504296307083091370 2268
UVM_ERROR @ 691588018 ps: (otp_ctrl_scoreboard.sv:691) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 691588018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 44867756042938330242271465961188221742853340367737479892401170784444578268059 232
UVM_ERROR @ 11045455084 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 11045455084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_check_fail 90639146096064387211408627370678484143851277482860074037972703069538541601906 858
UVM_ERROR @ 74730635 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 74730635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 58726410914793689964101317590956709859999643812508728407311850302294517614057 668
UVM_ERROR @ 155921568 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 155921568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 41845254728446035348340156283486316267846627087938832879853701893936819823216 1623
UVM_ERROR @ 143208260 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 143208260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 88999159271393303457136215932183135101697918077077937504431422571775126553765 157
UVM_ERROR @ 66024285 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 66024285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 105756094530616249289885430371295153353847401751460313409760488069468375296762 1240
UVM_ERROR @ 573009090 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 573009090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 46523485777144632418054660942164999730976731763847495013678610760980731566219 6540
UVM_ERROR @ 1120397480 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 1120397480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 13028037397027665494714446422437537055722914893996105476010359080531163648159 7065
UVM_ERROR @ 1499149883 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 1499149883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1308) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_init_fail 62745322511697040934325128534185538271668952656874841852598236028563458705514 1870
UVM_ERROR @ 1681671946 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1681671946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 90338284084896499051173991906922991982513656518832783714417906187981362118658 1596
UVM_ERROR @ 1564866005 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1564866005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 30004833874811601302118580696340619581234852999930715991975674958874723307352 896
UVM_ERROR @ 1251854722 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1251854722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 56641113249743952742471888984145174412153826851414766255834661872391036614241 2052
UVM_ERROR @ 933027071 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 933027071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 33715091873901480468101697898940909870409461531695890819943513760580472411226 1612
UVM_ERROR @ 1756494078 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1756494078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 16227724027558538511612938995603846441779334712371700485066177710838582525949 1082
UVM_ERROR @ 218013447 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 218013447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 45037160783682991820714139277510563323271175201410833638047847287892869976937 1594
UVM_ERROR @ 1905546974 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1905546974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106272405316054526936769705868902188761930894515994770428449252348257227553095 2130
UVM_ERROR @ 265305225 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 265305225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 89302365853052051620456453968888763709938958724359524235122685697125971357126 1456
UVM_ERROR @ 1480713795 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1480713795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 89954530722548279442600357330949125426413059968352011274065144953341071550034 1556
UVM_ERROR @ 375850970 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 375850970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22161525135189448816620330242038369676286192999672107164330167382670467497348 908
UVM_ERROR @ 1708275746 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1708275746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 2012679826068716978728122806238979113334875345784160981132710117993399683419 1694
UVM_ERROR @ 438594902 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 438594902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 57118809206812549419410356307526953099116370607161564736219402940734770413964 2336
UVM_ERROR @ 2254475715 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 2254475715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 37160542019453150443797007637115800032456975285260113094917013796436144439505 1490
UVM_ERROR @ 1075728552 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1075728552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77263762649161194371033962752916455821951864060694099063933665703102677867062 3224
UVM_ERROR @ 349994615 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 349994615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22303329599265634083245786570029894012707942209431038447977522820650273240547 1270
UVM_ERROR @ 271418288 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 271418288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 56791638007441793096804902347449821069029144320021767928698227627672244996761 1694
UVM_ERROR @ 207659182 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 207659182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106913293898144029783670703463764793015007417221069644354665586978582872957792 1724
UVM_ERROR @ 381194941 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 381194941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 16314620482316415236363902480263249083167326926538761300172773884477683194351 1672
UVM_ERROR @ 1518589935 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 1518589935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 89740966654261662141050734183227979748636495755194433700423717403268058141187 1664
UVM_ERROR @ 211254923 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 211254923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 84459237356927028542201794693341148342824002633114304739221869194040918426113 1070
UVM_ERROR @ 297917584 ps: (cip_base_vseq.sv:1308) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 297917584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_macro_errs 97847978936301453692699432892146748662617104568426955870030680513627286263269 15830
UVM_ERROR @ 1727202640 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
UVM_INFO @ 1727202640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---