Simulation Results: rom_ctrl

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
73.58%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.760s 297.949us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.920s 382.032us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.890s 172.317us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.550s 957.317us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 4.660s 871.106us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.400s 310.187us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.890s 172.317us 20 20 100.00
rom_ctrl_csr_aliasing 4.660s 871.106us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.830s 169.541us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.800s 246.451us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.960s 174.716us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 35.830s 4006.169us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 12.610s 307.191us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.140s 5578.070us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 11.280s 372.750us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 11.280s 372.750us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.920s 382.032us 5 5 100.00
rom_ctrl_csr_rw 6.890s 172.317us 20 20 100.00
rom_ctrl_csr_aliasing 4.660s 871.106us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.480s 178.192us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.920s 382.032us 5 5 100.00
rom_ctrl_csr_rw 6.890s 172.317us 20 20 100.00
rom_ctrl_csr_aliasing 4.660s 871.106us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.480s 178.192us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.310s 3309.893us 20 20 100.00
tl_intg_err 21 25 84.00
rom_ctrl_tl_intg_err 80.290s 282.082us 20 20 100.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
prim_fsm_check 1 5 20.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
prim_count_check 1 5 20.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
sec_cm_checker_ctr_consistency 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_checker_ctrl_flow_consistency 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_checker_fsm_local_esc 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_compare_ctrl_flow_consistency 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_compare_ctr_consistency 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_compare_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.760s 297.949us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.760s 297.949us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.760s 297.949us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 80.290s 282.082us 20 20 100.00
sec_cm_bus_local_esc 16 22 72.73
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
rom_ctrl_kmac_err_chk 12.610s 307.191us 2 2 100.00
sec_cm_mux_mubi 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_mux_consistency 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_ctrl_redun 14 20 70.00
rom_ctrl_corrupt_sig_fatal_chk 113.030s 12090.061us 14 20 70.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.310s 3309.893us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 284.070s 526.379us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 434.480s 4553.108us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 97937776702145738378387943993419030187558480218472489394910155433524647367961 430
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 144883447ps failed at 144883447ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 144883447ps failed at 144883447ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 100177775116599872296735469621255220211625703563947605086522245622480001615972 185
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26209649ps failed at 26209649ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26209649ps failed at 26209649ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 88260708522565319132565860156669838259856883994486861214783673600640945646619 246
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 17526298ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 17526298ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 17526298ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
rom_ctrl_sec_cm 83615312413554779364372546667110475187170296383872419445493773316617189677614 298
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 64509974ps failed at 64509974ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 71791535ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 71791535ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 14112251384569306584505651564877575152108650354895528483000161829455832432701 95
UVM_ERROR @ 1091329587 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1091329587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 109641510586308005900295583441027343289299287014946161249013327098693535902449 100
UVM_ERROR @ 1321433237 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1321433237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 62206092428795019265795079338404570110108212982215796027173809310209903601512 77
UVM_ERROR @ 667034164 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 667034164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 108393392030567297679406101453156135474341547464750644891941643846222741537564 77
UVM_ERROR @ 253901791 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 253901791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 25920869317559326121316546958226636042519844788627791303978413305010143225141 86
UVM_ERROR @ 2762979831 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2762979831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 5404462684138301501475730859475061702614648342588368507290477675234322522789 89
UVM_ERROR @ 2410418378 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2410418378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---