rom_ctrl Simulation Results

Simulation Results: rom_ctrl

14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.48 %

code
99.36 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.27 %

cond
98.07 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	9.390s	304.602us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	14.320s	963.518us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	17.350s	1068.972us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	17.970s	1076.878us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	10.100s	319.617us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	15.040s	1048.848us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	17.350s	1068.972us	20	20	100.00
	rom_ctrl_csr_aliasing	10.100s	319.617us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	12.100s	314.614us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	9.620s	908.207us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	10.940s	307.411us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	74.800s	4107.200us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	20.990s	1060.496us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	13.650s	4296.889us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	15.760s	290.410us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	15.760s	290.410us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.320s	963.518us	5	5	100.00
	rom_ctrl_csr_rw	17.350s	1068.972us	20	20	100.00
	rom_ctrl_csr_aliasing	10.100s	319.617us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.750s	4278.306us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.320s	963.518us	5	5	100.00
	rom_ctrl_csr_rw	17.350s	1068.972us	20	20	100.00
	rom_ctrl_csr_aliasing	10.100s	319.617us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.750s	4278.306us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	65.140s	22871.081us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_tl_intg_err	134.950s	849.856us	20	20	100.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	9.390s	304.602us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	9.390s	304.602us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	9.390s	304.602us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	134.950s	849.856us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
	rom_ctrl_kmac_err_chk	20.990s	1060.496us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	237.660s	23056.382us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	65.140s	22871.081us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	526.270s	1536.176us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	257.000s	18108.118us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	58113320594945126950377373330418778867702103966436484278497432856171832227081	117	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 17223323ps failed at 17223323ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17223323ps failed at 17223323ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	50873710803844955569211217327530909174511783822538977868033004466568985218166	303	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 77943243ps failed at 77943243ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 77943243ps failed at 77943243ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	47641603329952779764565746653556977985275646071841716904284114497509470209928	162	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 7902881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 7902881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 7902881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	93288327373304500647284536889554986932838020040037132823212060832891039085069	291	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13800709ps failed at 13800709ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13811126ps failed at 13811126ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'