Simulation Results: spi_host

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.65%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 109.000s 2725.521us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 52.380us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 113.331us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 3.000s 181.952us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 28.349us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 33.543us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 113.331us 20 20 100.00
spi_host_csr_aliasing 2.000s 28.349us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 37.399us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 1.000s 66.349us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 136.329us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 27.000s 2082.406us 50 50 100.00
spi_host_error_cmd 2.000s 34.141us 50 50 100.00
spi_host_event 264.000s 25214.670us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 520.474us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 520.474us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 520.474us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 232.000s 14546.251us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 24.017us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 520.474us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 520.474us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 109.000s 2725.521us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 109.000s 2725.521us 50 50 100.00
stress_all 49 50 98.00
spi_host_stress_all 2225.000s 1000000.000us 49 50 98.00
spien 50 50 100.00
spi_host_spien 339.000s 8842.440us 50 50 100.00
stall 47 50 94.00
spi_host_status_stall 1892.000s 1000000.000us 47 50 94.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 56.000s 2313.797us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 27.000s 2082.406us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 41.799us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 19.424us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 1821.079us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 1821.079us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 52.380us 5 5 100.00
spi_host_csr_rw 2.000s 113.331us 20 20 100.00
spi_host_csr_aliasing 2.000s 28.349us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 65.855us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 52.380us 5 5 100.00
spi_host_csr_rw 2.000s 113.331us 20 20 100.00
spi_host_csr_aliasing 2.000s 28.349us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 65.855us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 158.165us 5 5 100.00
spi_host_tl_intg_err 3.000s 172.616us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 172.616us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 707.000s 57398.189us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_status_stall 18104310649184695610504796731071603058744077419614101774742833692702396270691 3833
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 111812233431908083099079071804022079682401743105407261507205644143724586139292 8191
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 81348115390565017420377485514852418528341926269603766792591730988227722543561 267
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed
spi_host_status_stall 83796860686799585027838839014587018360402383953058407770606811594286421225891 763
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 2180018858 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 2180018858 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=2180019000 ps
UVM_INFO @ 2180018858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---