Simulation Results: sram_ctrl

 
14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.10%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 111.180s 7421.535us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 12.627us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.100s 26.053us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.700s 125.189us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.080s 44.140us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.460s 384.994us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.100s 26.053us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 44.140us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 380.400s 103519.903us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 195.540s 87562.358us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1343.350s 114441.104us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 450.420s 26010.004us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2343.560s 155736.755us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1433.160s 21518.081us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 134.320s 14976.820us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1724.690s 12341.608us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 110.750s 3828.732us 50 50 100.00
sram_ctrl_partial_access_b2b 584.700s 46614.311us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 101.940s 819.174us 50 50 100.00
sram_ctrl_throughput_w_partial_write 108.840s 15416.693us 50 50 100.00
sram_ctrl_throughput_w_readback 112.140s 5704.707us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1440.050s 19041.550us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 7.000s 6675.153us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7360.840s 930646.535us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.050s 31.497us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.230s 318.249us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.230s 318.249us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 12.627us 5 5 100.00
sram_ctrl_csr_rw 1.100s 26.053us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 44.140us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 24.027us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 12.627us 5 5 100.00
sram_ctrl_csr_rw 1.100s 26.053us 20 20 100.00
sram_ctrl_csr_aliasing 1.080s 44.140us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.170s 24.027us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 51.250s 7062.872us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
sram_ctrl_tl_intg_err 4.780s 2173.833us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.780s 2173.833us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1440.050s 19041.550us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1440.050s 19041.550us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.100s 26.053us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1724.690s 12341.608us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1724.690s 12341.608us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1724.690s 12341.608us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 134.320s 14976.820us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 44 50 88.00
sram_ctrl_mubi_enc_err 11.380s 7494.921us 44 50 88.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 51.250s 7062.872us 20 20 100.00
sec_cm_mem_readback 40 50 80.00
sram_ctrl_readback_err 11.830s 8300.006us 40 50 80.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 111.180s 7421.535us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 111.180s 7421.535us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1724.690s 12341.608us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 134.320s 14976.820us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 111.180s 7421.535us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.040s 51.975us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 235.470s 9108.963us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 62045774373621051312743887285793863979727018477335731466414479932705347060697 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 6076701 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 6076701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 10795150605737296181480996838257642238538421155764558458786354799896710074415 101
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4644623ps failed at 4644623ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 5399623 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5399623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 99882881572466128071722715543168830886079500639752777286463863102471142910945 96
UVM_ERROR @ 7395364 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7395364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 3591318447816313207501802938955473797694478017257527618373252202317542195798 102
UVM_ERROR @ 51975036 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 51975036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 27633908251656725899334951838344591653140186315008797542959532989725642980440 97
UVM_ERROR @ 11203080 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 11203080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 50965203566237360188095414271362747842812582845011337680746767394528239578214 95
UVM_ERROR @ 1349377645 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x5e)
UVM_INFO @ 1349377645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54219456429317894040001114213782035438249908843429798964630772589019545489698 95
UVM_ERROR @ 2751130229 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x60)
UVM_INFO @ 2751130229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 18996800788662780303014915249065034820653869351965042675457488844335900863142 95
UVM_ERROR @ 662144739 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x50) != exp (0x33)
UVM_INFO @ 662144739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 17566347576737995291327577545989204296663827214842181255182377672280372033987 95
UVM_ERROR @ 829020476 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x9)
UVM_INFO @ 829020476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 20118301525076993260997611787858114497369249071521320486611243089377838609041 95
UVM_ERROR @ 706341507 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x71) != exp (0x38)
UVM_INFO @ 706341507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 17545237691803671533011641194932764325513759994031380088389047430990018099291 95
UVM_ERROR @ 658743145 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x3d)
UVM_INFO @ 658743145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 56338223763222825150676022479864232313885354614491745708725200200631565672363 95
UVM_ERROR @ 5476481196 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xb) != exp (0x5b)
UVM_INFO @ 5476481196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 69547944748371914643381519891064928985224070417922736905511320116264712009829 95
UVM_ERROR @ 659083059 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4b) != exp (0x72)
UVM_INFO @ 659083059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 63638219400604416702887361848306373542164289404779001730189199026270458112224 95
UVM_ERROR @ 3284782851 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x3b)
UVM_INFO @ 3284782851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 452622513914499895355191086567089264618007892339314523302991738738034858199 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 720476047 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 720476047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 105400539742116359693005008374898396416355810907215390218342990799979258191875 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2758978631 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2758978631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 115560180988306328021476086811082953911705777390611474053190629612733847981323 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 9514445641 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 9514445641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 38735990268507767430394631197762328862594165722828194183518852826696443721616 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 667834425 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 667834425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 59827054659705466557212820664976780617346199198720497512472050556860429996008 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2350286600 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2350286600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 94351736902803702813716431204366586808617442383032094664805113302165058857513 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 686611207 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 686611207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4470) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_readback_err 61653851159704594798189407852722546078470408008918901189261723922146261901312 95
UVM_ERROR @ 2653276008 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4470) { a_addr: 'h57c3c4e4 a_data: 'h23 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h58 a_opcode: 'h0 a_user: 'h24272 d_param: 'h0 d_source: 'h58 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2653276008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---