sram_ctrl Simulation Results

Simulation Results: sram_ctrl

14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.81 %

code
96.12 %

assert
95.79 %

func
98.52 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.13%
V2		100.00%
V2S		93.97%
V3		100.00%

228/230 passed

99.13 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	79.720s	2070.330us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.030s	14.784us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.070s	38.587us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	2.090s	126.208us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.110s	17.030us	5	5	100.00
csr_mem_rw_with_rand_reset				18	20	90.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.800s	166.967us	18	20	90.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.070s	38.587us	20	20	100.00
	sram_ctrl_csr_aliasing	1.110s	17.030us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.870s	2741.559us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.710s	180.590us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1154.200s	30792.012us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	388.940s	4684.771us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	79.990s	4821.040us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1286.120s	9049.185us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	12.740s	4349.106us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1414.210s	23368.435us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	114.980s	230.183us	50	50	100.00
	sram_ctrl_partial_access_b2b	553.040s	155978.444us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	106.080s	261.766us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	94.980s	604.896us	50	50	100.00
	sram_ctrl_throughput_w_readback	107.050s	542.293us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1386.150s	16032.829us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.260s	387.225us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4323.230s	117053.022us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.060s	18.193us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.550s	840.949us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.550s	840.949us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	14.784us	5	5	100.00
	sram_ctrl_csr_rw	1.070s	38.587us	20	20	100.00
	sram_ctrl_csr_aliasing	1.110s	17.030us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	44.614us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	14.784us	5	5	100.00
	sram_ctrl_csr_rw	1.070s	38.587us	20	20	100.00
	sram_ctrl_csr_aliasing	1.110s	17.030us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.120s	44.614us	20	20	100.00

V2S

733/780 passed

93.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.830s	389.904us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00
	sram_ctrl_tl_intg_err	4.030s	4344.070us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	4.030s	4344.070us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1386.150s	16032.829us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1386.150s	16032.829us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.070s	38.587us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1414.210s	23368.435us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1414.210s	23368.435us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1414.210s	23368.435us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	12.740s	4349.106us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				46	50	92.00
	sram_ctrl_mubi_enc_err	1.680s	184.945us	46	50	92.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.830s	389.904us	20	20	100.00
sec_cm_mem_readback				37	50	74.00
	sram_ctrl_readback_err	1.630s	232.330us	37	50	74.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	79.720s	2070.330us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	79.720s	2070.330us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1414.210s	23368.435us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	12.740s	4349.106us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	79.720s	2070.330us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.040s	7.358us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	667.280s	9525.029us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	42678357291469798789146342386300433689123867084224533856071538103353207918207	97	UVM_ERROR @ 9592342 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 9592342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	19886670522788245716592705622558139015048800402636709225125961256267015277922	96	UVM_ERROR @ 4374942 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 4374942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	56301787682431653582392249617877054818366233591334793274756805886881761593648	95	UVM_ERROR @ 25129513 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x25) != exp (0x5b) UVM_INFO @ 25129513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	90713762776246557124558518010011310878496103749919139612569752879391822105329	95	UVM_ERROR @ 41453151 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x31) UVM_INFO @ 41453151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	40104334538855648850183132277178673929244991672981066067011079007546748924374	95	UVM_ERROR @ 28287821 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6a) != exp (0x75) UVM_INFO @ 28287821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	100942470591789401727865886096237308847796886694781188961212227868799867415994	95	UVM_ERROR @ 177334308 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x51) UVM_INFO @ 177334308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	53387508584995811905821049180659173257271125323100622496044137172569856071912	95	UVM_ERROR @ 26740752 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2d) != exp (0x37) UVM_INFO @ 26740752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	4164721216240545219609353854824876289600501491838198933768252959515294939634	95	UVM_ERROR @ 53112680 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2e) != exp (0x39) UVM_INFO @ 53112680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	67856739360053370451165738068850700081924360807505955512526361345911586620408	95	UVM_ERROR @ 97344958 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2d) != exp (0x31) UVM_INFO @ 97344958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	39547648617637543816839303280153278267665610551972670954493777887219330902988	95	UVM_ERROR @ 90670544 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x45) UVM_INFO @ 90670544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	105335309033258146245021482471085682596153486674591067824855415345065255059213	95	UVM_ERROR @ 25807723 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4a) != exp (0x2a) UVM_INFO @ 25807723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	71710774167351304527878227968304726976405853398398256762448786599904366092084	95	UVM_ERROR @ 23557188 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x32) != exp (0x30) UVM_INFO @ 23557188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	47729472368399947699084717591507632833434746293376531602623403987149306407570	95	UVM_ERROR @ 23655242 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x7f) UVM_INFO @ 23655242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	67103113538996102273466832823899176563929443785239601954717446771342673612794	95	UVM_ERROR @ 71490126 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x60) != exp (0x1e) UVM_INFO @ 71490126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	85304437973557947305121720866646713025744696447334301151091633379417924189309	95	UVM_ERROR @ 24495388 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x78) UVM_INFO @ 24495388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	6236109319535483935553477104005608923065706368801704568719548811848853625230	96	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 3696886 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 3696886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	106106709055980844173448191442978853681223131647922592043339760814568467511352	96	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 4261295 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 4261295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
	sram_ctrl_sec_cm	103710308953309600013030723261739824661778306947702049466908158134348031986838	102	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 7358226 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 7358226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	73493535466758290035275893255251103564949422220911656363110602140486503312393	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 94226326 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 94226326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	108315596583651209011496558635320428707594392924469394658768972990427678605744	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 85671042 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 85671042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	51895878650223675276960744110761367926064001168103295042716643862844287241338	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 47173151 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 47173151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	68100347696350530568089246799487237382249521913298255575913816409379780566931	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 77026800 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 77026800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	4118154689160933703606589446378671352770486387347578144656799157944420619195	95	UVM_ERROR @ 260735635 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 260735635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_csr_mem_rw_with_rand_reset	41788193934697160008977162550767166255849603151830367119321010231979964492603	95	UVM_ERROR @ 47811578 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9 UVM_INFO @ 47811578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---