sysrst_ctrl Simulation Results

Simulation Results: sysrst_ctrl

14/12/2025 00:12:36 sha: 801ac60 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
97.77 %

assert
98.18 %

func
87.28 %

line
98.90 %

branch
99.00 %

cond
97.98 %

toggle
100.00 %

FSM
92.95 %

Validation stages

V1		100.00%
V2		97.60%
V2S		100.00%
V3		96.00%

190/190 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sysrst_ctrl_smoke	8.730s	2109.136us	50	50	100.00
input_output_inverted				50	50	100.00
	sysrst_ctrl_in_out_inverted	10.700s	2462.870us	50	50	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	9.330s	2190.219us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	10.640s	2529.815us	5	5	100.00
csr_hw_reset				5	5	100.00
	sysrst_ctrl_csr_hw_reset	17.870s	6015.616us	5	5	100.00
csr_rw				20	20	100.00
	sysrst_ctrl_csr_rw	9.110s	2056.100us	20	20	100.00
csr_bit_bash				5	5	100.00
	sysrst_ctrl_csr_bit_bash	100.670s	41350.468us	5	5	100.00
csr_aliasing				5	5	100.00
	sysrst_ctrl_csr_aliasing	15.100s	3198.562us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	8.500s	2039.312us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sysrst_ctrl_csr_rw	9.110s	2056.100us	20	20	100.00
	sysrst_ctrl_csr_aliasing	15.100s	3198.562us	5	5	100.00

773/792 passed

97.60 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				50	50	100.00
	sysrst_ctrl_combo_detect	424.380s	157573.310us	50	50	100.00
combo_detect_with_pre_cond				95	100	95.00
	sysrst_ctrl_combo_detect_with_pre_cond	416.470s	217324.684us	95	100	95.00
auto_block_key_outputs				47	50	94.00
	sysrst_ctrl_auto_blk_key_output	664.840s	269355.291us	47	50	94.00
keyboard_input_triggered_interrupt				50	50	100.00
	sysrst_ctrl_edge_detect	181.410s	1246296.550us	50	50	100.00
pin_output_keyboard_inversion_control				50	50	100.00
	sysrst_ctrl_pin_override_test	10.830s	2513.548us	50	50	100.00
pin_input_value_accessibility				50	50	100.00
	sysrst_ctrl_pin_access_test	9.460s	2251.876us	50	50	100.00
ec_power_on_reset				49	50	98.00
	sysrst_ctrl_ec_pwr_on_rst	19.930s	5284.668us	49	50	98.00
flash_write_protect_output				50	50	100.00
	sysrst_ctrl_flash_wr_prot_out	10.920s	2610.790us	50	50	100.00
ultra_low_power_test				41	50	82.00
	sysrst_ctrl_ultra_low_pwr	275.180s	2055365.041us	41	50	82.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	93.000s	40196.058us	2	2	100.00
stress_all				49	50	98.00
	sysrst_ctrl_stress_all	1638.880s	1411802.590us	49	50	98.00
alert_test				50	50	100.00
	sysrst_ctrl_alert_test	8.230s	2010.691us	50	50	100.00
intr_test				50	50	100.00
	sysrst_ctrl_intr_test	8.160s	2011.124us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.260s	2054.040us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.260s	2054.040us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	17.870s	6015.616us	5	5	100.00
	sysrst_ctrl_csr_rw	9.110s	2056.100us	20	20	100.00
	sysrst_ctrl_csr_aliasing	15.100s	3198.562us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	28.020s	9010.367us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	17.870s	6015.616us	5	5	100.00
	sysrst_ctrl_csr_rw	9.110s	2056.100us	20	20	100.00
	sysrst_ctrl_csr_aliasing	15.100s	3198.562us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	28.020s	9010.367us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	sysrst_ctrl_sec_cm	116.490s	42012.656us	5	5	100.00
	sysrst_ctrl_tl_intg_err	100.570s	42406.006us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	sysrst_ctrl_tl_intg_err	100.570s	42406.006us	20	20	100.00

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				48	50	96.00
	sysrst_ctrl_stress_all_with_rand_reset	23.600s	6347.095us	48	50	96.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
	sysrst_ctrl_ultra_low_pwr	71506459362458694591405238497252052480269824405770131001368685863330959188316	648	UVM_ERROR @ 5739212685 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 5739233737 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5739233737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	101264529895047837148111457297912058353976331148339768585202506648986700955911	647	UVM_ERROR @ 4554568585 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4554659495 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4554659495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	86094371182385933288654268660905768591689217200276203284894397674239135375854	650	UVM_ERROR @ 9115710865 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 9115732843 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 9115732843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	72766135388141971410554046419591329891426556308334260864355675361240007705927	655	UVM_ERROR @ 14631163202 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 14631184254 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 14631184254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	5700554896036780773020013449336631000713246237741565002190505414961171757144	708	UVM_ERROR @ 63232296345 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1]) UVM_ERROR @ 63467563475 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1]) UVM_INFO @ 63467563475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [] vs [*])
	sysrst_ctrl_auto_blk_key_output	41698776226583599387272318323837316542403411574403688220394431066325008741300	649	UVM_ERROR @ 2177667759 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2292847563 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 18 UVM_INFO @ 2477667759 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:27 UVM_INFO @ 2578016511 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: b UVM_INFO @ 2687667759 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:12
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	66968357660053333028278564490977650499594617786966143815063411498561947719087	668	UVM_ERROR @ 26329061692 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4 UVM_INFO @ 26399061692 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 26419061692 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 36496446499 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x11 UVM_INFO @ 36496587913 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x19
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	33908042936255784572553718727552839464105112568929694388376077644339617998717	725	UVM_ERROR @ 25066302635 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 25066302635 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1]) UVM_INFO @ 25066302635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
	sysrst_ctrl_ultra_low_pwr	34205012355551927018527356690024485699049366581121078623880197516241258170411	647	UVM_ERROR @ 2433338923 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2520838923 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 7215838923 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 12535838923 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 12562235464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
	sysrst_ctrl_ultra_low_pwr	62424132297834910495291631301159996336405177607897961169614852014146209784653	648	UVM_ERROR @ 5356061682 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 5418561682 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_INFO @ 7623561682 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 7635678865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	60374217749293796941991306036793224998988151086248690671776715146734987897504	647	UVM_ERROR @ 2444106851 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2456606851 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_INFO @ 5481606851 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 5502092828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	88571396285697780797362914354728206149404810633320760012907025559405021167911	647	UVM_ERROR @ 3063599863 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 3196099863 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 3196099863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	85175878358756534404069750714697310254910147167018421019593256279860142149516	647	UVM_ERROR @ 3300839752 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 3608339752 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i UVM_INFO @ 3848339752 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 3968414041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	39538675495026550616189271031712125856175904519581428569979243618492200920084	647	UVM_ERROR @ 3878356067 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 4670856067 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 4670856067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	49210351474024537547949918692860323655748786628189258048152719161704750738878	719	UVM_ERROR @ 14291280515 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 14291280515 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 14291280515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (* [] vs [*])
	sysrst_ctrl_auto_blk_key_output	99262317964465826295932601542075915247964158134401458148872847392796883364617	649	UVM_ERROR @ 2529102645 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2629282295 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 12 UVM_INFO @ 2819102645 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:23 UVM_INFO @ 2924282295 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 50 UVM_INFO @ 3404102645 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:84
	sysrst_ctrl_auto_blk_key_output	5580981938749802298712546635767577747301724131188836285028560550460418996637	649	UVM_ERROR @ 2242436721 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2343113142 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 3e UVM_INFO @ 2737436721 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:70 UVM_INFO @ 2842705235 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 24 UVM_INFO @ 3152436721 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:40
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == *
	sysrst_ctrl_ec_pwr_on_rst	108679104697071294160540101664003112757731389874545405102036304828179652368027	647	UVM_FATAL @ 2985381201 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0 UVM_INFO @ 2985381201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	85782085982323288173587382735074064364610085684875012493515085009995254199687	681	UVM_ERROR @ 53355036613 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 63648210308 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d UVM_INFO @ 63648424592 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2c UVM_INFO @ 64165420456 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1 UVM_INFO @ 64165527598 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	27370771736081387849025628129482984978992478876012836412034205485669431399802	679	UVM_ERROR @ 29525219875 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(3) +/-4 UVM_INFO @ 39797606473 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x30 UVM_INFO @ 39798166473 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x26 UVM_INFO @ 40246646473 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2 UVM_INFO @ 40246646473 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	65690181167997015030047758335223789024219144554971288843202634147617042451090	657	UVM_ERROR @ 15952249052 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4 UVM_ERROR @ 15952249052 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(6) vs exp(2) +/-4 UVM_INFO @ 15952249052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---