Simulation Results: adc_ctrl

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.44 %
  • code
  • 98.74 %
  • assert
  • 95.95 %
  • func
  • 91.63 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 96.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.90%
V2S
100.00%
V3
96.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 20.890s 6069.394us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 3.140s 1329.306us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.660s 510.178us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 48.170s 51166.751us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 5.840s 722.678us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.700s 481.297us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.660s 510.178us 20 20 100.00
adc_ctrl_csr_aliasing 5.840s 722.678us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1280.810s 497118.556us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1491.670s 485690.887us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1122.240s 512493.392us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1131.960s 509364.131us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1351.850s 572734.584us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1472.250s 614141.049us 50 50 100.00
filters_both 46 50 92.00
adc_ctrl_filters_both 1497.700s 600000.000us 46 50 92.00
clock_gating 31 50 62.00
adc_ctrl_clock_gating 1098.580s 490634.621us 31 50 62.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 17.610s 5648.769us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 144.850s 45284.236us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 418.680s 128884.605us 50 50 100.00
stress_all 47 50 94.00
adc_ctrl_stress_all 1483.120s 718917.656us 47 50 94.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.440s 458.428us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.580s 507.179us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 4.270s 551.702us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 4.270s 551.702us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.140s 1329.306us 5 5 100.00
adc_ctrl_csr_rw 2.660s 510.178us 20 20 100.00
adc_ctrl_csr_aliasing 5.840s 722.678us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.300s 4400.717us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.140s 1329.306us 5 5 100.00
adc_ctrl_csr_rw 2.660s 510.178us 20 20 100.00
adc_ctrl_csr_aliasing 5.840s 722.678us 5 5 100.00
adc_ctrl_same_csr_outstanding 16.300s 4400.717us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 16.320s 7878.409us 5 5 100.00
adc_ctrl_tl_intg_err 27.560s 8404.768us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 27.560s 8404.768us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 48 50 96.00
adc_ctrl_stress_all_with_rand_reset 3459.320s 10000000.000us 48 50 96.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 55520201639912684489926806009259022472429537563449521768239946949906876683597 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 90367904405793893008519979422664438448042376526325469461135177432702671930693 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 8024130172229664297291208444808507205082980566679883102369663613005565568108 350
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 44561640974370688734613857844424340548462683718497763389096807146891201649687 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 58488001336669814483534146109173759062237057926778842495084984954667963786118 349
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 46781921065654125209310597037284247403057730499622588468479766316063977765612 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 63529158992455618954859759041852790623430097953102434715981171774692162336149 358
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 110890591522262649068008037100246471766492180588690294573282325749955414991764 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 62950702383981330789913545181641445732521377172828791278167136782395387185817 350
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 26480735595671953302013167473836419686472998553777112825916249441404300700735 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 39450155987117225970581422982210797288294628523812533686506404634158221241583 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 99285826016530044717602372968233565298497741836801789210169887211059255895891 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 80629302343201914587743238538439772270673218344873975671287246237589003945352 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 93944855972918292897269633398417079468882557933585870530354749980084668385278 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 78110000650675331805598345801693517860374721763667970850764328700573764283014 318
UVM_ERROR @ 4333616900 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4333616900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 103415150738866912363836960100049107675702152436717838760042810451794546782914 318
UVM_ERROR @ 3419074188 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3419074188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 19959013047756178947833915589267072851135529497271052361507747112898550234097 338
UVM_ERROR @ 210722106964 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 210722106964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 38632038316460058024785304981537984184665551496163805296451662332056380592291 318
UVM_ERROR @ 2894873940 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2894873940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 50514318439806409835226402420307199506852750134413816845015447991357739267988 335
UVM_ERROR @ 165603792493 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 165603792493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 103754874398537837241638626630569050734111352592003036504195492621364986910716 318
UVM_ERROR @ 1932690353 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1932690353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 9963402654399488653959873661563290465660514855088972815216169446134232908434 352
UVM_ERROR @ 421664580370 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 421664580370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 71690505835239885529593933270092201285249785015696386450474419039299443962195 335
UVM_ERROR @ 193065964870 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 193065964870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 51885557064130979613712791087364676966435942867396864240106321062536746232002 404
UVM_ERROR @ 189672611044 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 189672611044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_clock_gating 95097985502164864222078276842448635329257432208601789109630308091409799580474 352
UVM_ERROR @ 448229521005 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 448229521005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 35452518721109043240034657107353380868246454626729233418943347287389478431100 334
UVM_ERROR @ 325758457818 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 325758457818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 106106987013787499360605124655597535047868223516011474281797301035544987996188 319
UVM_ERROR @ 81533895309 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 81533895309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 16370650304553521006288396545797226620927336631987617103160504672454924147508 318
UVM_ERROR @ 82504171699 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 82504171699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:885) [random_ramp_vseq] timeout occurred!
adc_ctrl_clock_gating 63418405835021280181249878581254561583286394033978853682385954912549392172181 352
UVM_FATAL @ 468878882011 ps: (cip_base_vseq.sv:885) [uvm_test_top.env.virtual_sequencer.adc_ctrl_clock_gating_vseq.random_ramp_vseq] timeout occurred!
UVM_INFO @ 468878882011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---