clkmgr Simulation Results

Simulation Results: clkmgr

21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.43 %

code
99.01 %

assert
96.47 %

func
87.82 %

line
99.38 %

branch
99.27 %

cond
96.38 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		97.78%
V3		100.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	1.250s	17.435us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	1.230s	48.995us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	8.500s	1974.275us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	1.990s	93.140us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.740s	622.221us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
	clkmgr_csr_aliasing	1.990s	93.140us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.010s	21.039us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.730s	159.240us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	1.810s	439.649us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	1.200s	91.153us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	1.250s	17.435us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	13.350s	2480.322us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	12.110s	2057.497us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	13.350s	2480.322us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	68.060s	11888.136us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.260s	84.950us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	4.600s	967.257us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	4.600s	967.257us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	1.230s	48.995us	5	5	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
	clkmgr_csr_aliasing	1.990s	93.140us	5	5	100.00
	clkmgr_same_csr_outstanding	1.700s	208.519us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	1.230s	48.995us	5	5	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
	clkmgr_csr_aliasing	1.990s	93.140us	5	5	100.00
	clkmgr_same_csr_outstanding	1.700s	208.519us	20	20	100.00

V2S

572/585 passed

97.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				22	25	88.00
	clkmgr_sec_cm	2.530s	218.541us	2	5	40.00
	clkmgr_tl_intg_err	4.450s	1152.023us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.620s	245.394us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	2.620s	245.394us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.620s	245.394us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	2.620s	245.394us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	8.420s	3129.042us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	4.450s	1152.023us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	13.350s	2480.322us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	12.110s	2057.497us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	2.620s	245.394us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	1.920s	563.885us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.260s	105.230us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.440s	84.874us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				46	50	92.00
	clkmgr_clk_handshake_intersig_mubi	1.340s	91.790us	46	50	92.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.440s	322.062us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	2.530s	218.541us	2	5	40.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.150s	49.799us	20	20	100.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	2.530s	218.541us	2	5	40.00

100/100 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	5.550s	1266.147us	50	50	100.00
stress_all_with_rand_reset				50	50	100.00
	clkmgr_stress_all_with_rand_reset	129.980s	35435.959us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	21550518595522233362603485792118711346245563182718455955633476571902785970564	87	UVM_ERROR @ 26114070 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 26114070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	19272074548463337146912741107490053949914824305269638885290817176946965881618	77	UVM_ERROR @ 14312812 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 14312812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	52465600184559069266996611040849430394873961578991853692624603209238306845358	126	UVM_ERROR @ 218541357 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 218541357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	2839264034493072617423802884654741469709641575158009436052690363937903074671	71	UVM_ERROR @ 12472227 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (4 [0x4] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 12472227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	3390432164086375845749160604176064611356484262305944326944033984457266980275	71	UVM_ERROR @ 6272506 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (14 [0xe] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 6272506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	42185019285649140133744866394938873441666799173219160197829736417232973420493	71	UVM_ERROR @ 6185818 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (13 [0xd] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 6185818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	95067250339454526139234050532038211300745211178920680212678088047770886811337	71	UVM_ERROR @ 68234215 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (12 [0xc] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 68234215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---