Simulation Results: csrng

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.42 %
  • code
  • 96.32 %
  • assert
  • 95.85 %
  • func
  • 91.09 %
  • block
  • 98.72 %
  • line
  • 99.61 %
  • branch
  • 96.79 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.94%
V2S
99.98%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 6.000s 282.430us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 124.971us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 25.076us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 19.000s 1259.086us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 7.000s 479.249us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 114.283us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 25.076us 20 20 100.00
csrng_csr_aliasing 7.000s 479.249us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
alerts 500 500 100.00
csrng_alert 44.000s 3504.554us 500 500 100.00
err 500 500 100.00
csrng_err 8.000s 24.629us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 266.000s 25392.644us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 266.000s 25392.644us 50 50 100.00
stress_all 49 50 98.00
csrng_stress_all 977.000s 67475.364us 49 50 98.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 107.888us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 3.000s 47.649us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 14.000s 963.346us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 14.000s 963.346us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 124.971us 5 5 100.00
csrng_csr_rw 3.000s 25.076us 20 20 100.00
csrng_csr_aliasing 7.000s 479.249us 5 5 100.00
csrng_same_csr_outstanding 6.000s 208.691us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 124.971us 5 5 100.00
csrng_csr_rw 3.000s 25.076us 20 20 100.00
csrng_csr_aliasing 7.000s 479.249us 5 5 100.00
csrng_same_csr_outstanding 6.000s 208.691us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_tl_intg_err 11.000s 504.024us 20 20 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_config_regwen 70 70 100.00
csrng_csr_rw 3.000s 25.076us 20 20 100.00
csrng_regwen 3.000s 36.901us 50 50 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 44.000s 3504.554us 500 500 100.00
sec_cm_intersig_mubi 49 50 98.00
csrng_stress_all 977.000s 67475.364us 49 50 98.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 44.000s 3504.554us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
sec_cm_constants_lc_gated 49 50 98.00
csrng_stress_all 977.000s 67475.364us 49 50 98.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 44.000s 3504.554us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 11.000s 504.024us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
csrng_sec_cm 6.000s 393.169us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 14.000s 975.103us 200 200 100.00
csrng_err 8.000s 24.629us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 286.000s 8361.324us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 99519712882078694975216780918258225357838075498372920852709898150473713037258 158
UVM_ERROR @ 4680319721 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 4680319721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---