Simulation Results: edn

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 95.94 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 93.01 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.080s 19.430us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.890s 21.367us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.810s 16.424us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.220s 255.162us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.220s 153.993us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.400s 43.576us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.810s 16.424us 20 20 100.00
edn_csr_aliasing 1.220s 153.993us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 5.240s 927.058us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 5.240s 927.058us 300 300 100.00
genbits 300 300 100.00
edn_genbits 5.240s 927.058us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.230s 21.033us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.440s 292.901us 200 200 100.00
errs 100 100 100.00
edn_err 1.280s 101.551us 100 100 100.00
disable 100 100 100.00
edn_disable 1.110s 14.250us 50 50 100.00
edn_disable_auto_req_mode 1.550s 124.003us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.740s 373.360us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.840s 17.322us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.550s 78.666us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.340s 307.685us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.340s 307.685us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.890s 21.367us 5 5 100.00
edn_csr_rw 0.810s 16.424us 20 20 100.00
edn_csr_aliasing 1.220s 153.993us 5 5 100.00
edn_same_csr_outstanding 1.210s 150.465us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.890s 21.367us 5 5 100.00
edn_csr_rw 0.810s 16.424us 20 20 100.00
edn_csr_aliasing 1.220s 153.993us 5 5 100.00
edn_same_csr_outstanding 1.210s 150.465us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.220s 127.474us 20 20 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.930s 27.919us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.440s 292.901us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.440s 292.901us 200 200 100.00
edn_sec_cm 9.480s 1959.006us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.440s 292.901us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.220s 127.474us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 115.300s 27941.347us 50 50 100.00

Error Messages

   Test seed line log context