Simulation Results: edn

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 96.18 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.240s 45.093us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.050s 14.687us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.030s 18.361us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.310s 505.360us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.210s 275.893us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.500s 52.841us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.030s 18.361us 20 20 100.00
edn_csr_aliasing 1.210s 275.893us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 3.510s 498.172us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 3.510s 498.172us 300 300 100.00
genbits 300 300 100.00
edn_genbits 3.510s 498.172us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.370s 22.133us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.500s 51.325us 200 200 100.00
errs 100 100 100.00
edn_err 1.370s 19.000us 100 100 100.00
disable 100 100 100.00
edn_disable 1.180s 42.575us 50 50 100.00
edn_disable_auto_req_mode 1.380s 27.694us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.600s 229.206us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.020s 59.522us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.650s 94.774us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.150s 144.170us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.150s 144.170us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.050s 14.687us 5 5 100.00
edn_csr_rw 1.030s 18.361us 20 20 100.00
edn_csr_aliasing 1.210s 275.893us 5 5 100.00
edn_same_csr_outstanding 1.220s 25.626us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.050s 14.687us 5 5 100.00
edn_csr_rw 1.030s 18.361us 20 20 100.00
edn_csr_aliasing 1.210s 275.893us 5 5 100.00
edn_same_csr_outstanding 1.220s 25.626us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
edn_tl_intg_err 2.550s 212.257us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.280s 17.339us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.500s 51.325us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.500s 51.325us 200 200 100.00
edn_sec_cm 5.090s 377.191us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.500s 51.325us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.550s 212.257us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 100.560s 6303.324us 50 50 100.00

Error Messages

   Test seed line log context