flash_ctrl Simulation Results

Simulation Results: flash_ctrl

21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.92 %

code
95.80 %

assert
96.62 %

func
98.33 %

line
96.09 %

branch
97.45 %

cond
94.94 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		99.03%
V2S		99.64%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	137.710s	29.914us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	21.960s	36.447us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	39.540s	64.606us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	74.010s	12408.141us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	52.490s	11436.558us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.630s	56.677us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
	flash_ctrl_csr_aliasing	52.490s	11436.558us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.170s	17.186us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	11.760s	150.687us	5	5	100.00

1125/1136 passed

99.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	20.810s	26.793us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	80.060s	111.126us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1568.250s	85459.158us	3	3	100.00
	flash_ctrl_hw_rma_reset	787.690s	160202.536us	20	20	100.00
	flash_ctrl_lcmgr_intg	12.940s	22.572us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2104.120s	265480.491us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	378.910s	4848.441us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	218.370s	16675.140us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3226.320s	195649.863us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	135.350s	7144.166us	5	5	100.00
rd_buff_eviction_w_ecc				98	100	98.00
	flash_ctrl_rw_evict	31.890s	45.179us	39	40	97.50
	flash_ctrl_rw_evict_all_en	32.200s	30.936us	39	40	97.50
	flash_ctrl_re_evict	36.250s	81.469us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	232.510s	196.337us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	232.510s	196.337us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	804.780s	13302.450us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	27.090s	3782.588us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	605.590s	13787.228us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	656.500s	14871.415us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	558.120s	1185.818us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1301.970s	866.616us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.460s	41.107us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	188.760s	4021.998us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	21.230s	18.191us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.450s	17.985us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	706.100s	294.900us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	185.150s	17309.066us	50	50	100.00
	flash_ctrl_otp_reset	127.450s	83.270us	79	80	98.75
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1568.250s	85459.158us	3	3	100.00
interrupts				96	100	96.00
	flash_ctrl_intr_rd	183.150s	6327.557us	37	40	92.50
	flash_ctrl_intr_wr	91.150s	5211.254us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	492.640s	119449.904us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	321.900s	71187.186us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	72.390s	875.566us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	71.000s	677.411us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	21.760s	26.165us	5	5	100.00
	flash_ctrl_ro_derr	128.150s	1720.741us	10	10	100.00
	flash_ctrl_rw_derr	230.880s	2036.232us	10	10	100.00
	flash_ctrl_derr_detect	163.020s	2645.414us	5	5	100.00
	flash_ctrl_integrity	486.660s	4979.676us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	19.090s	48.777us	5	5	100.00
	flash_ctrl_ro_serr	126.850s	4911.556us	10	10	100.00
	flash_ctrl_rw_serr	186.930s	4082.542us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	68.970s	2995.178us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	102.840s	5160.729us	5	5	100.00
scramble				58	62	93.55
	flash_ctrl_wo	1357.700s	200000.000us	17	20	85.00
	flash_ctrl_write_word_sweep	7.370s	155.001us	1	1	100.00
	flash_ctrl_read_word_sweep	7.740s	328.455us	1	1	100.00
	flash_ctrl_ro	115.690s	2092.691us	19	20	95.00
	flash_ctrl_rw	516.920s	4813.927us	20	20	100.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	35.800s	1658.112us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	808.080s	104127.617us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	272.310s	10019.628us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.490s	463.625us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	12.610s	16.122us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	19.300s	246.337us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	19.300s	246.337us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	39.540s	64.606us	5	5	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
	flash_ctrl_csr_aliasing	52.490s	11436.558us	5	5	100.00
	flash_ctrl_same_csr_outstanding	36.040s	280.181us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	39.540s	64.606us	5	5	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
	flash_ctrl_csr_aliasing	52.490s	11436.558us	5	5	100.00
	flash_ctrl_same_csr_outstanding	36.040s	280.181us	20	20	100.00

V2S

820/823 passed

99.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	79.200s	501.282us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	546.210s	591.455us	20	20	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	546.210s	591.455us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	546.210s	591.455us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	25.310s	277.490us	3	3	100.00
	flash_ctrl_wr_intg	15.410s	361.526us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	137.710s	29.914us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				259	260	99.62
	flash_ctrl_otp_reset	127.450s	83.270us	79	80	98.75
	flash_ctrl_disable	21.230s	18.191us	50	50	100.00
	flash_ctrl_sec_info_access	80.540s	8505.924us	50	50	100.00
	flash_ctrl_connect	17.450s	17.985us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.160s	37.991us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.880s	35.853us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	68.860s	62.048us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	21.230s	18.191us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	25.310s	277.490us	3	3	100.00
	flash_ctrl_access_after_disable	12.760s	19.852us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	27.840s	160.802us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	21.230s	18.191us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	27.090s	3782.588us	10	10	100.00
sec_cm_mem_scramble				20	20	100.00
	flash_ctrl_rw	516.920s	4813.927us	20	20	100.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	186.930s	4082.542us	10	10	100.00
	flash_ctrl_rw_derr	230.880s	2036.232us	10	10	100.00
	flash_ctrl_integrity	486.660s	4979.676us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1568.250s	85459.158us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	19.910s	713.348us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				3	5	60.00
	flash_ctrl_phy_host_grant_err	11.040s	6.093us	3	5	60.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.650s	28.601us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2298.110s	2400.230us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	27.810s	74.586us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	564.260s	1638.844us	3	3	100.00

Error Messages

	Test	seed	line	log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	75272471660163719255048325070171608696547090174245313227848878399244990119900	122	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 19570.4 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 19570.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	23658936788575773832144320666044532759627981787046269690156918300107408635566	122	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 6093.3 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 6093.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	flash_ctrl_wo	32199883437584602240105862376315701951532201369210075181216542507926542752828	None	Job timed out after 60 minutes
	flash_ctrl_intr_wr	3629836235389973496413917464834491973434007699764908480903908291712860452151	None	Job timed out after 60 minutes
	flash_ctrl_wo	4685743889978008488286502368793297152817798970428325372620385606551400634128	None	Job timed out after 60 minutes
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp dd9d66f_20790cf0:ffffffff_20790cf* mismatch!!
	flash_ctrl_intr_rd	24622036755023561276875102423983005335244114014239632074364944657306520403390	105	UVM_ERROR @ 2632842.6 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 7: obs:exp 9dd9d66f_20790cf0:ffffffff_20790cf0 mismatch!! UVM_INFO @ 2632842.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly
	flash_ctrl_ro	79462453393395124627973181518490477910435934370181611672824838010719009744957	105	UVM_ERROR @ 193857.1 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 193857.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue
	flash_ctrl_wo	107605959513270235517549509000384845542641577403787113881947404817587545269573	105	UVM_FATAL @ 200000000.0 ns: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000.0 ns hit, indicating a probable testbench issue UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict_all_en	77771658038487700408330248480380886434706484945377877347160926952239352510772	105	UVM_ERROR @ 49139.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 49139.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	36891887652856489762477440439713044644061493454887393921115555774689288027390	105	UVM_ERROR @ 9038.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 9038.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp ab44_0a4120ba:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	115483492919352119612722780502227736352965312769479641707653646763508989812556	105	UVM_ERROR @ 1124514.4 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 2: obs:exp 1328ab44_0a4120ba:ffffffff_ffffffff mismatch!! UVM_INFO @ 1124514.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp d27e42f_94369c6c:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	80885348776761551393602227321116255046414776834308098418857657794983023316613	105	UVM_ERROR @ 5053974.9 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 3: obs:exp 2d27e42f_94369c6c:ffffffff_ffffffff mismatch!! UVM_INFO @ 5053974.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'
	flash_ctrl_otp_reset	15014927203238927984914540976922199049050023693378031277511882211413189266536	177	Offending 'dst_req_o' UVM_ERROR @ 15208.8 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 15208.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---