Simulation Results: hmac

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.78 %
  • code
  • 98.72 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.460s 5643.975us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.130s 112.508us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.360s 39.660us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 9.590s 425.396us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.130s 1796.803us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 816.030s 101743.422us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.360s 39.660us 20 20 100.00
hmac_csr_aliasing 7.130s 1796.803us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 77.880s 29023.384us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 83.450s 1651.798us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 244.270s 6680.282us 30 30 100.00
hmac_test_sha384_vectors 581.920s 177918.521us 75 75 100.00
hmac_test_sha512_vectors 528.290s 32573.649us 75 75 100.00
hmac_test_hmac256_vectors 14.890s 1369.289us 50 50 100.00
hmac_test_hmac384_vectors 17.920s 1603.414us 60 60 100.00
hmac_test_hmac512_vectors 20.080s 1482.139us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.760s 9600.586us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 962.020s 5632.797us 10 10 100.00
error 10 10 100.00
hmac_error 102.180s 86574.592us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 86.720s 14388.726us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.460s 5643.975us 10 10 100.00
hmac_long_msg 77.880s 29023.384us 10 10 100.00
hmac_back_pressure 83.450s 1651.798us 25 25 100.00
hmac_datapath_stress 962.020s 5632.797us 10 10 100.00
hmac_burst_wr 39.760s 9600.586us 50 50 100.00
hmac_stress_all 1631.760s 14812.491us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.460s 5643.975us 10 10 100.00
hmac_long_msg 77.880s 29023.384us 10 10 100.00
hmac_back_pressure 83.450s 1651.798us 25 25 100.00
hmac_datapath_stress 962.020s 5632.797us 10 10 100.00
hmac_wipe_secret 86.720s 14388.726us 10 10 100.00
hmac_test_sha256_vectors 244.270s 6680.282us 30 30 100.00
hmac_test_sha384_vectors 581.920s 177918.521us 75 75 100.00
hmac_test_sha512_vectors 528.290s 32573.649us 75 75 100.00
hmac_test_hmac256_vectors 14.890s 1369.289us 50 50 100.00
hmac_test_hmac384_vectors 17.920s 1603.414us 60 60 100.00
hmac_test_hmac512_vectors 20.080s 1482.139us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.460s 5643.975us 10 10 100.00
hmac_long_msg 77.880s 29023.384us 10 10 100.00
hmac_back_pressure 83.450s 1651.798us 25 25 100.00
hmac_datapath_stress 962.020s 5632.797us 10 10 100.00
hmac_burst_wr 39.760s 9600.586us 50 50 100.00
hmac_error 102.180s 86574.592us 10 10 100.00
hmac_wipe_secret 86.720s 14388.726us 10 10 100.00
hmac_test_sha256_vectors 244.270s 6680.282us 30 30 100.00
hmac_test_sha384_vectors 581.920s 177918.521us 75 75 100.00
hmac_test_sha512_vectors 528.290s 32573.649us 75 75 100.00
hmac_test_hmac256_vectors 14.890s 1369.289us 50 50 100.00
hmac_test_hmac384_vectors 17.920s 1603.414us 60 60 100.00
hmac_test_hmac512_vectors 20.080s 1482.139us 75 75 100.00
hmac_stress_all 1631.760s 14812.491us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1631.760s 14812.491us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.930s 19.179us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.940s 59.875us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.240s 201.557us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.240s 201.557us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.130s 112.508us 5 5 100.00
hmac_csr_rw 1.360s 39.660us 20 20 100.00
hmac_csr_aliasing 7.130s 1796.803us 5 5 100.00
hmac_same_csr_outstanding 3.090s 312.888us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.130s 112.508us 5 5 100.00
hmac_csr_rw 1.360s 39.660us 20 20 100.00
hmac_csr_aliasing 7.130s 1796.803us 5 5 100.00
hmac_same_csr_outstanding 3.090s 312.888us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 5.060s 1028.111us 20 20 100.00
hmac_sec_cm 1.400s 1040.981us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.060s 1028.111us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.460s 5643.975us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 9.700s 662.560us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 420.160s 17551.874us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.700s 746.657us 1 1 100.00

Error Messages

   Test seed line log context