Simulation Results: keymgr

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 99.01 %
  • assert
  • 97.72 %
  • func
  • 91.21 %
  • line
  • 99.13 %
  • branch
  • 99.10 %
  • cond
  • 98.18 %
  • toggle
  • 98.63 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.29%
V2S
99.32%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 36.590s 1502.386us 50 50 100.00
random 50 50 100.00
keymgr_random 48.150s 21881.671us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.480s 68.020us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 25.610s 5116.105us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 11.510s 377.301us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.780s 68.564us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
keymgr_csr_aliasing 11.510s 377.301us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 82.110s 7802.346us 49 50 98.00
sideload 200 200 100.00
keymgr_sideload 44.350s 3295.991us 50 50 100.00
keymgr_sideload_kmac 40.990s 5521.576us 50 50 100.00
keymgr_sideload_aes 26.260s 1654.674us 50 50 100.00
keymgr_sideload_otbn 30.180s 1139.336us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 29.190s 1170.976us 50 50 100.00
lc_disable 47 50 94.00
keymgr_lc_disable 7.490s 984.803us 47 50 94.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 8.450s 198.318us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 40.210s 1988.278us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 58.530s 2788.663us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 17.080s 4597.844us 50 50 100.00
stress_all 48 50 96.00
keymgr_stress_all 297.400s 13199.776us 48 50 96.00
intr_test 50 50 100.00
keymgr_intr_test 1.250s 52.827us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.420s 86.870us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.220s 618.886us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.220s 618.886us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.480s 68.020us 5 5 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
keymgr_csr_aliasing 11.510s 377.301us 5 5 100.00
keymgr_same_csr_outstanding 3.800s 1331.562us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.480s 68.020us 5 5 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
keymgr_csr_aliasing 11.510s 377.301us 5 5 100.00
keymgr_same_csr_outstanding 3.800s 1331.562us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
keymgr_tl_intg_err 9.070s 1222.090us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.360s 348.064us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.360s 348.064us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.360s 348.064us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.360s 348.064us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.350s 412.531us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.070s 1222.090us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.360s 348.064us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 82.110s 7802.346us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 48.150s 21881.671us 50 50 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 48.150s 21881.671us 50 50 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 48.150s 21881.671us 50 50 100.00
keymgr_csr_rw 1.540s 66.259us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 47 50 94.00
keymgr_lc_disable 7.490s 984.803us 47 50 94.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 58.530s 2788.663us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 58.530s 2788.663us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 48.150s 21881.671us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 8.860s 1852.238us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 19.760s 752.791us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 47 50 94.00
keymgr_lc_disable 7.490s 984.803us 47 50 94.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.760s 752.791us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.760s 752.791us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 19.760s 752.791us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 13.130s 724.256us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 19.760s 752.791us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
keymgr_stress_all_with_rand_reset 25.910s 7578.202us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 96615999628677422438002151760534183186186542782330080156801472423040345193961 139
UVM_ERROR @ 120931355 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120931355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95871415284267022998598013339485783969407667360083913053839767493621384914694 139
UVM_ERROR @ 122065664 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 122065664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23316904170024086560409939846763237225546426833824223149445152401056888847562 392
UVM_ERROR @ 140139416 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 140139416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 95288244085653195575576497660274853056138965839925742100916965017343169497298 134
UVM_ERROR @ 103700659 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 103700659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 22964026152076876188603419491271988628822799969277231681678620504260328154859 887
UVM_ERROR @ 4550743438 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4550743438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 8669185767353032821947568376515395907338118190976229076310892877633921457771 155
UVM_ERROR @ 501886085 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 501886085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 20267577534033112760014403865287176728854361064206711794429857333519164712929 324
UVM_ERROR @ 323644354 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 323644354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87317853008024254993973120337049158354756109166670909971804294744391306375493 408
UVM_ERROR @ 359784958 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 359784958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63359764496584347543493110205720924819669094608608049210399651781861485544726 171
UVM_ERROR @ 111892137 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111892137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61846879501842374190347329832487756982938622040427908955147265940822800631073 872
UVM_ERROR @ 473521767 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 473521767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 54514843569593314057690421431939954203373126748273193185171125065614160940275 1421
UVM_ERROR @ 2160357249 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2160357249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 39815183517644197646686213000781912931772012558029214560613324676130175039116 155
UVM_ERROR @ 571886562 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 571886562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 77972883302779738694139795588605821700301774294019480743087613560459100766584 195
UVM_ERROR @ 124098169 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 124098169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51948623729385875601194375729411082910204459675722275888640678759618372263742 145
UVM_ERROR @ 105533288 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 105533288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64912037953660968119603726554710882140451926257797128058182166021994796565232 1644
UVM_ERROR @ 7578202212 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7578202212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 4134200753110173676984450642261361712208908499439145632372811073329356941034 691
UVM_ERROR @ 583128663 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 583128663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83162989256783632246739676718248326659913207212041609467223149696652532437738 806
UVM_ERROR @ 557221901 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 557221901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 41331646590457950519550706127667954697302271240104033008974624821791158553026 191
UVM_ERROR @ 514507649 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 514507649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 883188602023867111578878184564241733858330076694006516222365410231435022014 374
UVM_ERROR @ 1340733764 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1340733764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 55477704849065064379903355646758373328001897000516522206111761146156843112356 866
UVM_ERROR @ 752403420 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 752403420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 83182261363623833814588749762928024886832588664028809777942883035809645059916 426
UVM_ERROR @ 1020108670 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1020108670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 79720495734382833434497944737730969031721712006036362683002370551536241586926 253
UVM_ERROR @ 622330112 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 622330112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 6995479357021688986726224592824911277980393518486629461525543614933662018912 792
UVM_ERROR @ 472144117 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 472144117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 45197058391608890370668647905967859298741869366755254786423823134340878197096 2337
UVM_ERROR @ 937556812 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 937556812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 12895406708663527203031241428424716972993125702947506459044854300942924074308 95
UVM_ERROR @ 13590516 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 13590516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 77610151978746389929318177243559145916056014984559642606611668891424662842653 251
UVM_ERROR @ 85116203 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 85116203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 21411895492063098458387299531655392550567588360160914668031540695319267051275 714
UVM_ERROR @ 1031215778 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1031215778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all 108553476750673649505404859225215286605441461971944177156747545481396563546306 278
UVM_ERROR @ 248618004 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (700039595 [0x29b9c1ab] vs 700039595 [0x29b9c1ab]) reg name: keymgr_reg_block.sw_share0_output_5
UVM_INFO @ 248618004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 88412876816088471726398338191393993951484959182206074440343635062362202706697 226
UVM_ERROR @ 79821806 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 79821806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes
keymgr_lc_disable 1422443534332328530897094565578975967489030941617106421387505397092589108419 556
UVM_ERROR @ 30696380 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1695164052605324058685290951201471887365723864884499096359511228559688054087042465882759022678354146599759824700619174275800630853250889622472592057882002 [0x205dca0eece134d9658a72e87e6bd7711ccf6f796fffec0cc3ab5ec1bac50e409d52b65b2b7625f52f6f65caba5d2402a85c725482f2ae2ee7f606745b8ad592] vs 1695164052605324058685290951201471887365723864884499096359511228559688054087042465882759022678354146599759824700619174275800630853250889622472592057882002 [0x205dca0eece134d9658a72e87e6bd7711ccf6f796fffec0cc3ab5ec1bac50e409d52b65b2b7625f52f6f65caba5d2402a85c725482f2ae2ee7f606745b8ad592]) AES key at state StCreatorRootKey for Attestation Aes
UVM_INFO @ 30696380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---