Simulation Results: kmac

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 94.35 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
99.29%
V2
99.29%
V2S
99.39%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
kmac_smoke 99.110s 35849.848us 49 50 98.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.420s 17.904us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.550s 39.299us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.830s 1471.097us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 10.100s 1602.332us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.170s 547.215us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.550s 39.299us 20 20 100.00
kmac_csr_aliasing 10.100s 1602.332us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.090s 40.391us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.730s 88.049us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3732.140s 129669.029us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1316.230s 37146.773us 50 50 100.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 2241.070s 1038185.548us 5 5 100.00
kmac_test_vectors_sha3_256 42.410s 2187.902us 5 5 100.00
kmac_test_vectors_sha3_384 1898.950s 278956.960us 5 5 100.00
kmac_test_vectors_sha3_512 1199.330s 128784.669us 4 5 80.00
kmac_test_vectors_shake_128 2359.400s 96421.572us 5 5 100.00
kmac_test_vectors_shake_256 2148.710s 365846.116us 5 5 100.00
kmac_test_vectors_kmac 3.550s 1179.820us 5 5 100.00
kmac_test_vectors_kmac_xof 3.670s 131.390us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 479.860s 85559.351us 50 50 100.00
app 50 50 100.00
kmac_app 322.440s 13335.939us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 326.020s 18320.389us 10 10 100.00
entropy_refresh 48 50 96.00
kmac_entropy_refresh 369.530s 73388.677us 48 50 96.00
error 50 50 100.00
kmac_error 459.910s 15522.737us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 17.190s 8621.705us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.410s 2979.529us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 48.040s 2710.580us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.100s 4104.200us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 76.750s 7140.367us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 43.770s 1855.883us 50 50 100.00
stress_all 47 50 94.00
kmac_stress_all 2180.250s 63293.876us 47 50 94.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 86.740us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.350s 264.397us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.390s 148.687us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.390s 148.687us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.420s 17.904us 5 5 100.00
kmac_csr_rw 1.550s 39.299us 20 20 100.00
kmac_csr_aliasing 10.100s 1602.332us 5 5 100.00
kmac_same_csr_outstanding 3.280s 536.236us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.420s 17.904us 5 5 100.00
kmac_csr_rw 1.550s 39.299us 20 20 100.00
kmac_csr_aliasing 10.100s 1602.332us 5 5 100.00
kmac_same_csr_outstanding 3.280s 536.236us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 96.189us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.640s 96.189us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 96.189us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.640s 96.189us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 5.590s 184.966us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.880s 1010.570us 20 20 100.00
kmac_sec_cm 88.940s 29216.479us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.880s 1010.570us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 43.770s 1855.883us 50 50 100.00
sec_cm_sw_key_key_masking 49 50 98.00
kmac_smoke 99.110s 35849.848us 49 50 98.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 479.860s 85559.351us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.640s 96.189us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 88.940s 29216.479us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 88.940s 29216.479us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 88.940s 29216.479us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 49 50 98.00
kmac_smoke 99.110s 35849.848us 49 50 98.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 43.770s 1855.883us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 88.940s 29216.479us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 392.730s 13590.493us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 49 50 98.00
kmac_smoke 99.110s 35849.848us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 215.180s 9658.199us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 87110398039449467687637901143768854328646005200050119410753235326048992274817 285
UVM_ERROR @ 9658199209 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 9658199209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 56875410209161711504449143767315545306527930709658557441165825985461752446334 419
UVM_ERROR @ 3274770746 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 3274770746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_test_vectors_sha3_512 96801470010520695546929909404751896187895665174165756672792172936882606718823 75
UVM_ERROR @ 29894759 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 29894759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 31868825056095217335436280943800137635830068262337599526045025368030797191299 77
UVM_ERROR @ 38005208 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 38005208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 71827608645804629282873230409243125325167284068922127661109371305912703952647 147
UVM_ERROR @ 11036445753 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 11036445753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 50073520841917154434332864417974035386563948884528461743217021114015683928587 225
UVM_ERROR @ 22309342915 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 22309342915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 9545062129733305630923749204880017033974019809050254512760079792510430095432 169
UVM_ERROR @ 15776411657 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 15776411657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 64994709731574654315880662231967640627148479769911785885173821361590890003436 204
UVM_ERROR @ 30854371832 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 30854371832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_smoke 24795516154487455275688631418338621901801747083190374172894107708054237604899 74
UVM_ERROR @ 69137288 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 69137288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 8655084457991636380655251318430136699167061319976624877964266437235167994103 124
UVM_ERROR @ 2908144454 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2908144454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---