Simulation Results: kmac

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.37 %
  • code
  • 91.97 %
  • assert
  • 97.74 %
  • func
  • 96.40 %
  • line
  • 97.59 %
  • branch
  • 95.97 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 71.90 %
Validation stages
V1
100.00%
V2
98.33%
V2S
99.60%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 84.850s 53826.926us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.530s 60.970us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.460s 119.851us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 9.670s 552.680us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.370s 390.522us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.910s 172.145us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.460s 119.851us 20 20 100.00
kmac_csr_aliasing 7.370s 390.522us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.080s 21.086us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.690s 51.931us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2753.440s 680120.826us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 774.230s 24495.658us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1252.880s 44997.593us 5 5 100.00
kmac_test_vectors_sha3_256 1745.310s 92123.083us 5 5 100.00
kmac_test_vectors_sha3_384 1121.160s 185934.286us 5 5 100.00
kmac_test_vectors_sha3_512 742.050s 129899.531us 5 5 100.00
kmac_test_vectors_shake_128 2026.480s 656528.418us 5 5 100.00
kmac_test_vectors_shake_256 1752.480s 152765.756us 5 5 100.00
kmac_test_vectors_kmac 2.450s 34.684us 5 5 100.00
kmac_test_vectors_kmac_xof 2.990s 142.914us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 333.810s 41029.343us 50 50 100.00
app 50 50 100.00
kmac_app 279.470s 35920.611us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 212.780s 12745.408us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 300.810s 69653.384us 50 50 100.00
error 50 50 100.00
kmac_error 422.560s 21462.186us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 13.120s 2099.119us 50 50 100.00
sideload_invalid 36 50 72.00
kmac_sideload_invalid 157.340s 10141.398us 36 50 72.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 30.930s 2872.611us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.550s 1467.947us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 77.680s 14495.263us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 45.110s 3302.008us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 1872.090s 515069.567us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.300s 34.472us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.300s 527.149us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.410s 309.389us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.410s 309.389us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.530s 60.970us 5 5 100.00
kmac_csr_rw 1.460s 119.851us 20 20 100.00
kmac_csr_aliasing 7.370s 390.522us 5 5 100.00
kmac_same_csr_outstanding 3.530s 387.266us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.530s 60.970us 5 5 100.00
kmac_csr_rw 1.460s 119.851us 20 20 100.00
kmac_csr_aliasing 7.370s 390.522us 5 5 100.00
kmac_same_csr_outstanding 3.530s 387.266us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 4.040s 256.295us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 4.040s 256.295us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 4.040s 256.295us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 4.040s 256.295us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 5.220s 807.115us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.930s 178.201us 20 20 100.00
kmac_sec_cm 57.610s 6211.983us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.930s 178.201us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 45.110s 3302.008us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 84.850s 53826.926us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 333.810s 41029.343us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 4.040s 256.295us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 57.610s 6211.983us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 57.610s 6211.983us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 57.610s 6211.983us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 84.850s 53826.926us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 45.110s 3302.008us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 57.610s 6211.983us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 9 10 90.00
kmac_mubi 323.730s 30735.356us 9 10 90.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 84.850s 53826.926us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 142.020s 6181.944us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 55526016613241844659981532133192600823229481133865845671842739792698121687291 230
UVM_ERROR @ 308852853 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1179235581 [0x4649b4fd] vs 8393187 [0x8011e3]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
UVM_INFO @ 308852853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 2282097519931277473298678832280630343308267257969416369081306331843281640504 75
UVM_FATAL @ 10038838329 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1fa51000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10038838329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 38130001015379384029444461131422051893210579823241220502234633703209326834505 75
UVM_FATAL @ 10034911809 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5b61d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10034911809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 63480663350188569248191739859599000160561185182507275893316560548940577681680 75
UVM_FATAL @ 10013028042 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf231000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10013028042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14725231199782577416172959455204008816081333025093639624798197248595157264877 75
UVM_FATAL @ 10008817232 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcf39c000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008817232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 33425229611108087961025742337218566907930275270785479106438439438477569838568 342
UVM_ERROR @ 9076668507 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9076668507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 73225000847064824126292603248102699624993035281820587940512738107927653479281 95
UVM_ERROR @ 1410818065 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1410818065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 12471716982466777135294760582522863774270884112977432068216030206686675428770 173
UVM_ERROR @ 11708464496 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11708464496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 104421324840272406611764522702729175100091043948250394316205404834977678621977 90
UVM_FATAL @ 10226167329 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x744a7000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10226167329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_mubi 49757090473672882684946439598285513369581600894307168184832506166699616536853 216
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 104907945432177160504077157180680000790029277989456864108361237927388957688106 79
UVM_FATAL @ 10037470536 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x22e40000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10037470536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 114771894954673344041348559938156329787295555491364282396109788222510185141145 78
UVM_FATAL @ 10024081150 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc1ef6000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10024081150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 16096932096433996324364921216268852615005774349993494684060598536194568693382 77
UVM_FATAL @ 10183789505 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6820d000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10183789505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 43158258135523190646158297737305608686391784992492521967603857913564489099945 83
UVM_FATAL @ 11501083226 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x34795000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 11501083226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 81533706346328541429559998069067618083703156660104565489937189251806521264865 80
UVM_FATAL @ 10053066665 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfe226000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10053066665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 74548303656872448349089837589380428376505441463477748075373365751716153489944 90
UVM_FATAL @ 10141398095 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x52b88000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10141398095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 42645945441658208878657447177360776312549472122976258716518981686100878017179 81
UVM_FATAL @ 10322161247 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2453b000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10322161247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 28006177655508738163214515801910434535163864813697922438036119738837791823263 87
UVM_FATAL @ 10190678015 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x13367000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10190678015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 29150212158822812767287044145995404018840650779118384014952603013458580048938 85
UVM_FATAL @ 10201508791 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdbedf000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10201508791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---