Simulation Results: otbn

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.71 %
  • code
  • 97.06 %
  • assert
  • 90.06 %
  • func
  • 100.00 %
  • block
  • 99.59 %
  • line
  • 99.68 %
  • branch
  • 95.37 %
  • toggle
  • 93.18 %
  • FSM
  • 100.00 %
Validation stages
V1
98.95%
V2
99.42%
V2S
95.98%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 21.000s 72.079us 1 1 100.00
single_binary 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 14.000s 45.796us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 157.743us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 10.000s 34.556us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 12.000s 35.468us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 12.000s 130.301us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 157.743us 20 20 100.00
otbn_csr_aliasing 12.000s 35.468us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 56.000s 1242.225us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 22.000s 504.873us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 43.000s 1184.654us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 333.155us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 117.000s 394.552us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 135.000s 1076.685us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 76.000s 264.585us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 22.737us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 37.000s 229.586us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 7.000s 24.955us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 36.284us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 10.000s 38.104us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 10.000s 38.104us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 14.000s 45.796us 5 5 100.00
otbn_csr_rw 8.000s 157.743us 20 20 100.00
otbn_csr_aliasing 12.000s 35.468us 5 5 100.00
otbn_same_csr_outstanding 7.000s 36.511us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 14.000s 45.796us 5 5 100.00
otbn_csr_rw 8.000s 157.743us 20 20 100.00
otbn_csr_aliasing 12.000s 35.468us 5 5 100.00
otbn_same_csr_outstanding 7.000s 36.511us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 44.150us 10 10 100.00
otbn_dmem_err 19.000s 81.695us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 9.000s 110.448us 5 5 100.00
otbn_controller_ispr_rdata_err 9.000s 61.373us 5 5 100.00
otbn_mac_bignum_acc_err 13.000s 183.771us 5 5 100.00
otbn_urnd_err 6.000s 10.272us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 10.000s 37.897us 5 5 100.00
otbn_mem_gnt_acc_err 1 2 50.00
otbn_mem_gnt_acc_err 19.000s 10012.444us 1 2 50.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 7.000s 23.094us 9 10 90.00
tl_intg_err 23 25 92.00
otbn_tl_intg_err 44.000s 205.655us 20 20 100.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 39.000s 209.011us 18 20 90.00
prim_fsm_check 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
prim_count_check 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 21.000s 72.079us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 19.000s 81.695us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 44.150us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 44.000s 205.655us 20 20 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 76.000s 264.585us 58 60 96.67
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 12.000s 44.150us 10 10 100.00
otbn_dmem_err 19.000s 81.695us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 22.737us 5 5 100.00
otbn_illegal_mem_acc 10.000s 37.897us 5 5 100.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_controller_fsm_sparse 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_scramble_key_sideload 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 12.000s 44.150us 10 10 100.00
otbn_dmem_err 19.000s 81.695us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 22.737us 5 5 100.00
otbn_illegal_mem_acc 10.000s 37.897us 5 5 100.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_scramble_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 76.000s 264.585us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 12.000s 44.150us 10 10 100.00
otbn_dmem_err 19.000s 81.695us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 22.737us 5 5 100.00
otbn_illegal_mem_acc 10.000s 37.897us 5 5 100.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_data_reg_sw_sca 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 13.000s 42.666us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 7.000s 30.394us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 44.000s 112.707us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 44.000s 112.707us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 114.627us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_stack_wr_ptr_ctr_redun 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 64.765us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_loop_stack_ctr_redun 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 24.501us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 10.000s 24.501us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 6 7 85.71
otbn_sec_wipe_err 7.000s 36.550us 6 7 85.71
sec_cm_data_mem_sec_wipe 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_instruction_mem_sec_wipe 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_data_reg_sw_sec_wipe 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 117.000s 394.552us 10 10 100.00
sec_cm_ctrl_flow_count 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_ctrl_flow_sca 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 17.000s 44.053us 5 5 100.00
sec_cm_key_sideload 98 100 98.00
otbn_single 247.000s 1090.029us 98 100 98.00
sec_cm_tlul_fifo_ctr_redun 3 5 60.00
otbn_sec_cm 955.000s 4340.941us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 484.000s 1751.754us 4 10 40.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 53520595971928736493875087350835176138273862167030808905431200468983371541398 168
UVM_FATAL @ 1260742631 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1260742631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 115551301383598023810219692159097027879217753119044107577777231684734985408286 103
UVM_FATAL @ 38335362 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 38335362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_single 111362903863895163450225647431768754520778128799994913359544334740409739228924 108
UVM_FATAL @ 25700307 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 25700307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_single 12827185927094470508053269422017757944426177658814192938748799385984068211754 107
UVM_FATAL @ 45218525 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 45218525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 54607451898459200165339210821050941859959834156057864253772973107435033505130 319
UVM_ERROR @ 2839880571 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2839880571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 63952183175424163645511542406613462270749577919424014429204405193489812731047 88
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 10508841 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 10508841 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 10508841 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 10508841 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 10508841 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 8356441303487105131920157483042118208450640228826112788381699333314958903270 100
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 17998886 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 17998886 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 17998886 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 17998886 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 17998886 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 105545231454627652134607096354573695105053870263866792183365115191008659186116 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36549535 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 36549535 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 36549535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 13671424713844101449852230785610270797983516615147990688146897453603729140461 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 80431151 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 80431151 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 80431151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 43666823517319185381991993551216821879657027168974088626487830636171451435599 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 151551649 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 151551649 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 151551649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred!
otbn_mem_gnt_acc_err 76349582552267737946297804595641169423575577344698688629507162952553144273679 108
UVM_FATAL @ 10012443582 ps: (otbn_mem_gnt_acc_err_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.otbn_mem_gnt_acc_err_vseq] timeout occurred!
UVM_INFO @ 10012443582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 114265806231356507682487008962993327375647772349678828695452563164818315478841 391
UVM_FATAL @ 3131365012 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 3131365012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 43416855634031845919769757163068228722143037420056641581015832306023244775535 502
UVM_FATAL @ 1751754400 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 1751754400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 95528501482544296368820198781870162229098507114154760795003580881463753498602 273
UVM_FATAL @ 384807873 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 384807873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 83198521175073628940415781818589372079362268599053402246506908881732757167808 246
UVM_FATAL @ 371418659 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 371418659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1021) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire
otbn_stress_all_with_rand_reset 102681206855384798250491897012425056433869330666136059661448651350824133261592 531
UVM_ERROR @ 2847779879 ps: (cip_base_vseq.sv:1021) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] expect alert:fatal to fire
UVM_INFO @ 2847779879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed
otbn_partial_wipe 47801361857931781499679576559062612590281587417087431539585680249398967215242 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 14028567 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
UVM_ERROR @ 14028567 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 14028567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---