| V1 |
|
100.00% |
| V2 |
|
87.95% |
| V2S |
|
100.00% |
| V3 |
|
6.00% |
| unmapped |
|
80.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 29.000s | 57.102us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 25.397us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 16.101us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| pattgen_csr_bit_bash | 3.000s | 647.717us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| pattgen_csr_aliasing | 2.000s | 34.788us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 40.984us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 16.101us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 34.788us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 32 | 50 | 64.00 | |||
| pattgen_perf | 3526.000s | 600000.000us | 32 | 50 | 64.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 83.000s | 2459.651us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 29.000s | 57.125us | 50 | 50 | 100.00 | |
| stress_all | 15 | 50 | 30.00 | |||
| pattgen_stress_all | 10383.000s | 1422825.515us | 15 | 50 | 30.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| pattgen_alert_test | 29.000s | 33.585us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| pattgen_intr_test | 2.000s | 182.249us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 225.729us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 225.729us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 25.397us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 16.101us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 34.788us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 54.805us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 25.397us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 16.101us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 34.788us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 54.805us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| pattgen_sec_cm | 29.000s | 160.354us | 5 | 5 | 100.00 | |
| pattgen_tl_intg_err | 2.000s | 484.660us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 484.660us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 50 | 6.00 | |||
| pattgen_stress_all_with_rand_reset | 118.000s | 5252.078us | 3 | 50 | 6.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 40 | 50 | 80.00 | |||
| pattgen_inactive_level | 267.000s | 10026.561us | 40 | 50 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| pattgen_perf | 87288949313403944869713158625845305270499262377699543906972315923428895658148 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_stress_all | 19658174612067460177804345254720589137146375295174064132084326056937491086330 | 110 |
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 3486556681152237947324607274623222251640979477558369761216894098052348278908 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 113584215808920391870094557990116474373616463544522239457217435590744949273785 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 88997612447825222814954287701366054791211998412492303893198712338500759234959 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 6827284361501813949708610519569184373241230570149627064255117411659320588540 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 106281460797539209966300068556728475498138080820008231388865395820724664771330 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 108859448782607412392447433609861924622868791848515602119276450795973801766560 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 32213716652791548445764157177130568477052476095703364191986108089498909854156 | 96 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) | ||||
| pattgen_inactive_level | 18553784265392054005776102812002886428616746201702816260018878267681479063585 | 96 |
UVM_FATAL @ 10003026029 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1476f810, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10003026029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| pattgen_stress_all_with_rand_reset | 71255815012082221985912188110899477354746237741337864048586729255353264083858 | 110 |
UVM_ERROR @ 460291555 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 460302964 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 460302964 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 460427965 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 69676560408346967698899248410573338703602164616652794244134453566125112002244 | 113 |
UVM_ERROR @ 2767760997 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2767790142 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2767790142 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 2768290140 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 97556613089856413829259396304349652786690778645824465017500979368519175842135 | 117 |
UVM_ERROR @ 1087338612 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1087344579 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1087344579 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1087446619 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115784271250266483802757333040230946742212374150948389892033040009313409723779 | 113 |
UVM_ERROR @ 7439358148 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 7439397462 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7439397462 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 7440683175 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 40957332120988299925560635835382507652262049235140472967645836089023137667339 | 165 |
UVM_ERROR @ 258426277 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 258426534 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 258426534 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 258530704 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 102624340427449648854748739597104587484564890818619901907941831319582688285887 | 169 |
UVM_ERROR @ 2826057204 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2826111663 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2826111663 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 2826464607 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 83147204814561412904147326902910510149031376852145755435489512899008777349016 | 164 |
UVM_ERROR @ 6185713864 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 6185770552 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6185770552 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 6186520549 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 73614899938562623788773071867698721803868620639789557473256448853297064836511 | 153 |
UVM_ERROR @ 14236290783 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 14236398794 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 14236398794 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 14237398793 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 102215637941214539246472647135732944659807213770696767080741105282256610257013 | 117 |
UVM_ERROR @ 1871596087 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1871605851 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1871605851 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1871789523 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 54782767626267470708618502004166149154251324527270623282401840876006686322431 | 162 |
UVM_ERROR @ 1555657645 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1555658454 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1555658454 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1555698454 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75385010850910590976490542963347928876148313025163386032747358602951711271217 | 178 |
UVM_ERROR @ 137724998 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 137731603 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 137731603 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 137806069 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 105057245824027435633368003012601285955807115386203816977592843333297002751016 | 222 |
UVM_ERROR @ 1237218424 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1237229764 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1237229764 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1237271430 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 11912829137148619306505491311007954340590177343847056380948519360695272433898 | 165 |
UVM_ERROR @ 10727481159 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 10727504047 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 10727504047 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 10728337377 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 7748047477180246297322408831569237837513455097178275644616325529986318473343 | 194 |
UVM_ERROR @ 1698873714 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1698874059 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1698874059 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1698966840 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 32773391040663988567425170227780945828168327549883731605365031050435309557578 | 251 |
UVM_ERROR @ 1157154561 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1157159615 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1157159615 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 1157232534 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115612779690860258776058202096444429688060693963105392693587598100617750881708 | 173 |
UVM_ERROR @ 2963886061 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2963891999 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2963891999 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 2964017000 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51364594742569601891662119836975116065865968943169849371409510145380639834023 | 120 |
UVM_ERROR @ 1857259658 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1857267418 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1857267418 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1857475748 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 25246201457203154536310951981699349890467888937838632821011575150439096966491 | 374 |
UVM_ERROR @ 2391762793 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2391766265 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2391766265 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 2391797516 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 59736982157033172506370302912668902808686212509891660199832666325393997795566 | 116 |
UVM_ERROR @ 478613015 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 478614612 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 478614612 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 478714612 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108183396224692761258655991838837472472342940992423656449435131115232800592701 | 319 |
UVM_ERROR @ 1792448480 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1792455365 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1792455365 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 7/10
UVM_INFO @ 1792485977 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 25617203276693306104804881192545592989843279437258229768243380042843807722365 | 112 |
UVM_ERROR @ 408540281 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 408541736 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 408541736 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 408635489 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 98065727022041936377539518895219124756946968581319235120390214935063144930437 | 261 |
UVM_ERROR @ 6244208519 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 6244215240 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6244215240 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 6244415238 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 3135858212159079144475221006571461803570285917029407282913752647480364106813 | 176 |
UVM_ERROR @ 1060012906 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1060014027 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1060014027 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1060076529 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115179281020262297635193906066337752362888666432589669842404915160667101593093 | 172 |
UVM_ERROR @ 1053232173 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1053234619 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1053234619 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1053255453 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 112411578736058913245099806560663870166339938641920638351162165453522922294914 | 194 |
UVM_ERROR @ 2814057955 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2814058856 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2814058856 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 2814143964 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 80395520426725714378954984957810064095858116591536407998660071958245423181730 | 189 |
UVM_ERROR @ 4545406873 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 4545448143 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4545448143 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 4545531477 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31240707647384814534882464906951526067986850589016525560952259578412871405530 | 121 |
UVM_ERROR @ 2025442946 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2025457665 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2025457665 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2025537665 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 94528209932826996153847442563500264421169078606818199321958584671512125101676 | 110 |
UVM_ERROR @ 115107839 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 115108715 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 115108715 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 115178715 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 83291568120258213006962553880187951226767054566014592408777110679910487845455 | 135 |
UVM_ERROR @ 441402577 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 441404042 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 441404042 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 441476205 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 49652062410991312195555035494790760996722743077835379370219853708837100657104 | 163 |
UVM_ERROR @ 3839734459 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3839750583 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3839750583 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3839870583 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 31832608443629648538721768309270684282268086095465967577067512842098867225090 | 140 |
UVM_ERROR @ 817456078 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 817457590 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 817457590 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 817518814 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 92874068850459937724430435132130044100909394139491819899377218967833118913784 | 113 |
UVM_ERROR @ 2605795289 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 2605797919 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2605797919 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 2605877919 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 11517015406976823090849686256138100314227055410545354959051463616768049082686 | 166 |
UVM_ERROR @ 597489178 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 597498008 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 597498008 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 597582216 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 9581731418189724522224181298519900153648336945583500042480874755705545376709 | 153 |
UVM_ERROR @ 1601825576 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1601841405 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1601841405 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1601901405 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 79763349029394722459281437274079934670160296127664567705925819395491714434539 | 142 |
UVM_ERROR @ 1883590013 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1883590565 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1883590565 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1883632231 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 24517872537330745106179224964236068153940186316779095492727175442692904645349 | 164 |
UVM_ERROR @ 925060892 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 925080067 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 925080067 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 925225898 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 60183046222029335905406834704543120537299588736798252171534219113641773232650 | 110 |
UVM_ERROR @ 437634533 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 437662410 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 437662410 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 437787411 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 91888059011653604280328836984621181901995513056123368950061719933545698353122 | 159 |
UVM_ERROR @ 13725926764 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 13725982362 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 13725982362 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 13726399027 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 47786350173873695466236240203865312265319527914525403887425436492540035862572 | 408 |
UVM_ERROR @ 8778210453 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 8778243959 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8778243959 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 8778493961 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 81233851375201714460276303477519243355840633900370574777060841865809103167079 | 229 |
UVM_ERROR @ 3286535405 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3286587782 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3286587782 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 3286798310 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 99838980386127736670969814513766039106272275906802711920376451874353760534893 | 128 |
UVM_ERROR @ 1828279786 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1828285499 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1828285499 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1828389664 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 21699298278128733793707342587780561627583983844261672776863306121609823930367 | 152 |
UVM_ERROR @ 4308492649 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 4308503692 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4308503692 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 4309195999 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 30700389204307179309269882467040761268083648407636239401769924200079890819318 | 110 |
UVM_ERROR @ 407629818 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 407645338 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 407645338 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 407722262 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 22391696492801314191122227254968015538298923695153942468655468854717814341735 | 110 |
UVM_ERROR @ 215277194 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 215277986 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 215277986 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 215486316 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 73569508643519636077543639820761619427920665110194329247298193256640973776885 | 207 |
UVM_ERROR @ 23954054752 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 23954064084 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 23954064084 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 23955564087 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 3105658414037396472280967112350891970975192017946019766151300943398381479726 | 209 |
UVM_ERROR @ 561448473 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 561451537 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 561451537 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 561511537 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 68201048018408779855057207380004980182419913308683789960401026288842628855277 | 110 |
UVM_ERROR @ 433816428 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 433836979 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 433836979 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 433920313 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) | ||||
| pattgen_inactive_level | 60720713356269840753879661169170004427418014903927938119334247881889231551468 | 96 |
UVM_FATAL @ 10096559558 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9a8c80d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10096559558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 53901244270078155887889164732415431603481645328497588281837476017859625348898 | 96 |
UVM_FATAL @ 10044388231 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6c8a3350, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10044388231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 29421686814048605224592237140518323919514549161125953304490858575345786462020 | 96 |
UVM_FATAL @ 10008258176 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x51209d10, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10008258176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| pattgen_stress_all | 7122464860796759226007949061225730497116219875233729398977557678909673506398 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 8061460528939856679980140935343523595956544550605521181935318726707097243113 | None |
Job timed out after 60 minutes
|
|
| pattgen_perf | 101778689324003668093932629172800644731860473912390200405704443323568727461615 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 14850397172578294555955030354203909187253832658886727567826235261070767611745 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 55336374149153510342274334308803975578975808754603197322323000307112851017728 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 11267749439786606608198170203478742903365439209136362370417412394071559187182 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 85202617941746049283796965769707735021327420979691209060116090530465163749690 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 93386909787667952849374275301333413615776366632580702509736825854528409654598 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 100740405752820335927264603955805678940464679270656977874342483512254342990063 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 3871360609876843247007401308603240750112340897556194124737120800004816837527 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 73139835144139846312112557761773559142744251939278444938900911884711777105472 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 18105549019239660475134882317913415112292819987832765334262763609873700432252 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 103105998867254477997728115021227360420135947560327845753237549702297732331138 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 1008152443148337717646031684894310211658971238287467019233124994846429748100 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 35687227254536433990877973167955564277773356145575159502391746202391242353356 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 110629129055083522096977953184756424262016001957093546543725910237062825851928 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 111325098720213365534214806142970514235017956828416040089547402255286526790471 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 30603778010669180604258116165861937771685354986869090885276920783799249738357 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 54425148948975511981643236252579920348156602215444399716736548660197801582959 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 53112637006393128035505914005728968532654831220551172771099897702577695329135 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 68179077901988432688165387055393337745420351666003383838524996363686311634033 | None |
Job timed out after 180 minutes
|
|
| pattgen_stress_all | 27589068512038006880475643641825157288183685976652650782459399089276786306099 | None |
Job timed out after 180 minutes
|
|
| pattgen_perf | 36137928064834471600646905136209387801613227585575300107329113452305982543858 | None |
Job timed out after 60 minutes
|
|
| pattgen_perf | 84436103506319129079057838022239505905091644886574957178307364100778587203563 | None |
Job timed out after 60 minutes
|
|
| pattgen_stress_all | 65904183632385565143955851423521306005507633017951561241055431089443380606430 | None |
Job timed out after 180 minutes
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | ||||
| pattgen_stress_all | 23808343840689559850924924418993424001555450110057322739888164254595858432830 | 132 |
UVM_ERROR @ 186431753 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10173
|
|
| pattgen_stress_all | 103033191984148181118385666604257110417159628510261273767061034532595860171970 | 122 |
UVM_ERROR @ 37668123157 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @10345
|
|
| pattgen_stress_all | 55248189798171529443641964926151009748865899366865822031749455682870169276419 | 127 |
UVM_ERROR @ 87962116 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
-------------------------------------
Name Type Size Value
-------------------------------------
exp_item pattgen_item - @10202
|
|
| pattgen_stress_all | 92111359904695501848099566195711827935934526449463683519731051248539699989160 | 143 |
UVM_ERROR @ 4021221150 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10281
|
|
| pattgen_stress_all | 10878798644158371419610200033506070999572603468483814416792874321173091464723 | 139 |
UVM_ERROR @ 128786839272 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10314
|
|
| pattgen_stress_all | 30019948692917123794883384858776590745889675941523559617646273813579244577951 | 145 |
UVM_ERROR @ 639088905 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10211
|
|
| pattgen_stress_all | 12698108863099530957072299648794531747969565037462275547397932359012222284908 | 135 |
UVM_ERROR @ 21099343414 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @10773
|
|
| pattgen_stress_all | 89360585369747932499019334647505097230150779838657622382831787669844541249870 | 132 |
UVM_ERROR @ 1395045285186 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10210
|
|
| pattgen_stress_all | 28628606140319382071030423008924203941856321782620522873075932756664866108687 | 127 |
UVM_ERROR @ 268477420 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10199
|
|
| pattgen_stress_all | 6024358741841008629227276914733824160768812937510981760363418646184232388576 | 122 |
UVM_ERROR @ 120355623 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10181
|
|
| pattgen_stress_all | 540995068952108151733541457151753440519073567557348131670716401814795700043 | 141 |
UVM_ERROR @ 21931141066 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11833
|
|
| pattgen_stress_all | 75133900635049418972660567653557508766798232460767077455010214718538341729150 | 133 |
UVM_ERROR @ 113324831 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10138
|
|
| pattgen_stress_all | 6749307687605730347585105064304179150941057306997931516349976176677883658305 | 156 |
UVM_ERROR @ 8165753967130 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10223
|
|
| pattgen_stress_all | 85602373158274487869386297858312092040492260930665476543062026170268314104472 | 146 |
UVM_ERROR @ 6236795967 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10334
|
|
| pattgen_stress_all | 68312378761097517428308476821323415628177876290784700724376095512233193425100 | 138 |
UVM_ERROR @ 172149911 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10177
|
|
| pattgen_stress_all | 50357114644281379859715804754205116697485709235761671100669294350916640844367 | 145 |
UVM_ERROR @ 158967740 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10190
|
|
| pattgen_stress_all | 71524013564228265835402129230342213120406931853376904372806889824191660305269 | 140 |
UVM_ERROR @ 1767213441 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10194
|
|
| pattgen_stress_all | 78062969628203255091731249759858694135162372593694532196823382508547290924404 | 122 |
UVM_ERROR @ 16492761296 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10198
|
|
| pattgen_stress_all | 54017990334968187296230321893753421606247667510590617905971162657602089753499 | 140 |
UVM_ERROR @ 5752117429 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @10387
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | ||||
| pattgen_inactive_level | 62941443494442781929309240907630387550470981447891320349542301474782416483411 | 96 |
UVM_FATAL @ 10006278848 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x205b7990, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10006278848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) | ||||
| pattgen_inactive_level | 108991259083754502181335609359687064882083361623566522148486043658819773941461 | 96 |
UVM_FATAL @ 10078774047 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc6828f10, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
UVM_INFO @ 10078774047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | ||||
| pattgen_inactive_level | 56562673612206821376945343791044311061296502359261204774428211550383461745801 | 96 |
UVM_FATAL @ 10113478550 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd9794c10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10113478550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | ||||
| pattgen_inactive_level | 65465296645930457693271707255744854819496601413452178392088537309817212044291 | 96 |
UVM_FATAL @ 10025499959 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xb1e712d0, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10025499959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | ||||
| pattgen_inactive_level | 57799951561660536859601270669748754184147143646027419182543884207678597147673 | 96 |
UVM_FATAL @ 10009900621 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xca869d50, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10009900621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) | ||||
| pattgen_inactive_level | 22676676951404299423492751154045824851049206668194202432219793461055695767028 | 96 |
UVM_FATAL @ 10026561029 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd90bb050, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10026561029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|