rom_ctrl Simulation Results

Simulation Results: rom_ctrl

21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.68 %

code
98.74 %

assert
95.49 %

func
98.81 %

line
99.46 %

branch
99.27 %

cond
95.39 %

toggle
99.59 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		77.99%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	6.920s	517.037us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	8.400s	2115.563us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	6.650s	166.213us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	6.030s	351.886us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	6.050s	557.122us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	7.450s	315.987us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	6.650s	166.213us	20	20	100.00
	rom_ctrl_csr_aliasing	6.050s	557.122us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	5.600s	559.054us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	7.130s	170.021us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.690s	746.721us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	30.000s	611.994us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	10.900s	576.590us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	8.130s	1043.669us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	10.430s	609.860us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	10.430s	609.860us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.400s	2115.563us	5	5	100.00
	rom_ctrl_csr_rw	6.650s	166.213us	20	20	100.00
	rom_ctrl_csr_aliasing	6.050s	557.122us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.630s	184.991us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	8.400s	2115.563us	5	5	100.00
	rom_ctrl_csr_rw	6.650s	166.213us	20	20	100.00
	rom_ctrl_csr_aliasing	6.050s	557.122us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.630s	184.991us	20	20	100.00

V2S

248/318 passed

77.99 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.110s	3100.179us	20	20	100.00
tl_intg_err				20	25	80.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00
	rom_ctrl_tl_intg_err	76.920s	536.627us	20	20	100.00
prim_fsm_check				0	5	0.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00
prim_count_check				0	5	0.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_compare_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00
sec_cm_fsm_sparse				0	5	0.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	6.920s	517.037us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	6.920s	517.037us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	6.920s	517.037us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	76.920s	536.627us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
	rom_ctrl_kmac_err_chk	10.900s	576.590us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	192.420s	50233.976us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	33.110s	3100.179us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	260.970s	554.669us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	469.840s	10006.981us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	45367964308481666054050039888470855832742433600275656585952121887569124225802	75	UVM_ERROR @ 415611458 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 415611458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	98057167519970704371537718808420789160919020382569811487286318583965644607940	101	UVM_ERROR @ 1237556844 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1237556844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	84800762897943410630728099780526761785095614296111092248118709036664206929324	79	UVM_ERROR @ 1199342191 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1199342191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	14197707467207134920882426697603541868599522353304472783925264092092993792659	93	UVM_ERROR @ 10971376286 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 10971376286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	45973638434872730492614526830155198414800370287485320987174178269699341366366	489	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29897760ps failed at 29897760ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 29907760ps failed at 29907760ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	24609802797568443829455214849269224678387951411350064687362917027664663139231	300	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 16614536ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 16614536ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 16614536ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	51409830534817812730960960362549345014924242215217344640113114145384867228209	115	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 7013296ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 7013296ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 7013296ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	9326095453032764420654320796011948014920818768984040591349743476348837735257	182	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 9656881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 9656881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 9656881ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
	rom_ctrl_sec_cm	114617532397356186323569639888265741278904773205747873432992136384176119805573	233	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11008032ps failed at 11008032ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11018236ps failed at 11018236ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'