Simulation Results: rom_ctrl

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.11%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 11.280s 227.584us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 16.780s 301.671us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 10.180s 544.545us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 12.370s 1943.202us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 11.590s 1074.911us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.320s 5071.209us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 10.180s 544.545us 20 20 100.00
rom_ctrl_csr_aliasing 11.590s 1074.911us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 9.560s 305.493us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 9.400s 589.447us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 19.060s 2116.176us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 58.690s 3049.116us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 23.090s 754.958us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 17.230s 2093.996us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 13.280s 1038.363us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 13.280s 1038.363us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 16.780s 301.671us 5 5 100.00
rom_ctrl_csr_rw 10.180s 544.545us 20 20 100.00
rom_ctrl_csr_aliasing 11.590s 1074.911us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.330s 1044.205us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 16.780s 301.671us 5 5 100.00
rom_ctrl_csr_rw 10.180s 544.545us 20 20 100.00
rom_ctrl_csr_aliasing 11.590s 1074.911us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.330s 1044.205us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 61.780s 24778.127us 20 20 100.00
tl_intg_err 24 25 96.00
rom_ctrl_tl_intg_err 175.590s 499.870us 20 20 100.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
prim_fsm_check 4 5 80.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
prim_count_check 4 5 80.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_compare_ctr_redun 4 5 80.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
sec_cm_fsm_sparse 4 5 80.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 11.280s 227.584us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 11.280s 227.584us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 11.280s 227.584us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 175.590s 499.870us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
rom_ctrl_kmac_err_chk 23.090s 754.958us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 253.590s 3765.907us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 61.780s 24778.127us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 4 5 80.00
rom_ctrl_sec_cm 557.030s 672.844us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 404.070s 9371.089us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 107965452459135801161675775584068526286497015122942471260656163254497770519192 186
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 9804961ps failed at 9804961ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 9804961ps failed at 9804961ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'