Simulation Results: rstmgr

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.85 %
  • code
  • 99.66 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.720s 251.954us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 0.850s 146.866us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 7.330s 2271.629us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.680s 355.918us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.340s 187.485us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00
rstmgr_csr_aliasing 1.680s 355.918us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.110s 139.743us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.220s 527.569us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.450s 270.327us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 5.630s 2063.042us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 5.630s 2063.042us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 5.630s 2063.042us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 5.630s 2063.042us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 39.920s 12302.591us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.220s 261.209us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.520s 481.035us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.520s 481.035us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 0.850s 146.866us 5 5 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00
rstmgr_csr_aliasing 1.680s 355.918us 5 5 100.00
rstmgr_same_csr_outstanding 1.380s 231.454us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 0.850s 146.866us 5 5 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00
rstmgr_csr_aliasing 1.680s 355.918us 5 5 100.00
rstmgr_same_csr_outstanding 1.380s 231.454us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 2.620s 900.081us 20 20 100.00
rstmgr_sec_cm 26.220s 21439.582us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.220s 21439.582us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.220s 21439.582us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 2.620s 900.081us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.300s 171.028us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.440s 2446.374us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.370s 302.574us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.220s 21439.582us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.830s 80.861us 20 20 100.00

Error Messages

   Test seed line log context