spi_device Simulation Results

Simulation Results: spi_device

21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.98 %

code
94.28 %

assert
94.41 %

func
99.26 %

line
99.17 %

branch
98.49 %

cond
96.66 %

toggle
87.74 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		99.95%
V2S		100.00%
unmapped		96.00%

140/140 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_device_flash_and_tpm	332.310s	449201.365us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_device_csr_hw_reset	1.680s	48.044us	5	5	100.00
csr_rw				20	20	100.00
	spi_device_csr_rw	2.850s	87.459us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_device_csr_bit_bash	32.080s	3768.041us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_device_csr_aliasing	18.860s	709.914us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_device_csr_mem_rw_with_rand_reset	3.830s	457.521us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_device_csr_rw	2.850s	87.459us	20	20	100.00
	spi_device_csr_aliasing	18.860s	709.914us	5	5	100.00
mem_walk				5	5	100.00
	spi_device_mem_walk	1.030s	14.562us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_device_mem_partial_access	2.570s	270.476us	5	5	100.00

2160/2161 passed

99.95 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				50	50	100.00
	spi_device_csb_read	1.180s	22.083us	50	50	100.00
mem_parity				20	20	100.00
	spi_device_mem_parity	1.460s	133.278us	20	20	100.00
mem_cfg				1	1	100.00
	spi_device_ram_cfg	1.140s	15.159us	1	1	100.00
tpm_read				50	50	100.00
	spi_device_tpm_rw	7.120s	852.822us	50	50	100.00
tpm_write				50	50	100.00
	spi_device_tpm_rw	7.120s	852.822us	50	50	100.00
tpm_hw_reg				100	100	100.00
	spi_device_tpm_read_hw_reg	28.790s	30365.622us	50	50	100.00
	spi_device_tpm_sts_read	1.430s	399.596us	50	50	100.00
tpm_fully_random_case				50	50	100.00
	spi_device_tpm_all	38.570s	7850.569us	50	50	100.00
pass_cmd_filtering				100	100	100.00
	spi_device_pass_cmd_filtering	43.270s	43350.778us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
pass_addr_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	39.640s	10758.426us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
pass_payload_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	39.640s	10758.426us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_info_slots				50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_read_status				100	100	100.00
	spi_device_intercept	27.330s	6066.521us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_read_jedec				100	100	100.00
	spi_device_intercept	27.330s	6066.521us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_read_sfdp				100	100	100.00
	spi_device_intercept	27.330s	6066.521us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_fast_read				100	100	100.00
	spi_device_intercept	27.330s	6066.521us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
cmd_read_pipeline				100	100	100.00
	spi_device_intercept	27.330s	6066.521us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
flash_cmd_upload				50	50	100.00
	spi_device_upload	33.270s	22992.268us	50	50	100.00
mailbox_command				50	50	100.00
	spi_device_mailbox	127.270s	51398.374us	50	50	100.00
mailbox_cross_outside_command				50	50	100.00
	spi_device_mailbox	127.270s	51398.374us	50	50	100.00
mailbox_cross_inside_command				50	50	100.00
	spi_device_mailbox	127.270s	51398.374us	50	50	100.00
cmd_read_buffer				100	100	100.00
	spi_device_flash_mode	57.800s	7517.596us	50	50	100.00
	spi_device_read_buffer_direct	17.570s	6948.155us	50	50	100.00
cmd_dummy_cycle				100	100	100.00
	spi_device_mailbox	127.270s	51398.374us	50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
quad_spi				50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
dual_spi				50	50	100.00
	spi_device_flash_all	397.250s	79403.157us	50	50	100.00
4b_3b_feature				50	50	100.00
	spi_device_cfg_cmd	33.380s	4003.603us	50	50	100.00
write_enable_disable				50	50	100.00
	spi_device_cfg_cmd	33.380s	4003.603us	50	50	100.00
TPM_with_flash_or_passthrough_mode				50	50	100.00
	spi_device_flash_and_tpm	332.310s	449201.365us	50	50	100.00
tpm_and_flash_trans_with_min_inactive_time				49	50	98.00
	spi_device_flash_and_tpm_min_idle	671.140s	77834.758us	49	50	98.00
stress_all				50	50	100.00
	spi_device_stress_all	649.150s	267943.658us	50	50	100.00
alert_test				50	50	100.00
	spi_device_alert_test	1.130s	16.686us	50	50	100.00
intr_test				50	50	100.00
	spi_device_intr_test	1.100s	62.385us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_device_tl_errors	5.160s	92.507us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_device_tl_errors	5.160s	92.507us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_device_csr_hw_reset	1.680s	48.044us	5	5	100.00
	spi_device_csr_rw	2.850s	87.459us	20	20	100.00
	spi_device_csr_aliasing	18.860s	709.914us	5	5	100.00
	spi_device_same_csr_outstanding	4.130s	226.725us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_device_csr_hw_reset	1.680s	48.044us	5	5	100.00
	spi_device_csr_rw	2.850s	87.459us	20	20	100.00
	spi_device_csr_aliasing	18.860s	709.914us	5	5	100.00
	spi_device_same_csr_outstanding	4.130s	226.725us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_device_tl_intg_err	19.260s	1580.864us	20	20	100.00
	spi_device_sec_cm	1.650s	82.183us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_device_tl_intg_err	19.260s	1580.864us	20	20	100.00

unmapped

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				48	50	96.00
	spi_device_flash_mode_ignore_cmds	500.020s	311024.004us	48	50	96.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [] vs []) flash_status.busy == expected to be *
	spi_device_flash_mode_ignore_cmds	105901700627926577069608676129631411048323673238628423567297801318945087637636	104	UVM_ERROR @ 1555103803 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0 UVM_INFO @ 1578763132 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/7 UVM_INFO @ 1607839213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [] vs []) CSR last_read_addr compare mismatch act != exp *
	spi_device_flash_and_tpm_min_idle	110342310565174204817462916205437249864599272156484952557269765432657324519252	106	UVM_ERROR @ 4765970956 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (13904896 [0xd42c00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xd42c00 != exp 0x0 tl_ul_fuzzy_flash_status_q[i] = 0x12474 tl_ul_fuzzy_flash_status_q[i] = 0x12474 tl_ul_fuzzy_flash_status_q[i] = 0x83eb0c tl_ul_fuzzy_flash_status_q[i] = 0x7b6ca0
	spi_device_flash_mode_ignore_cmds	60357324109419192317134261851269359466513261256803024448164263595716560459725	76	UVM_ERROR @ 1172872860 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14891008 [0xe33800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xe33800 != exp 0x0 UVM_INFO @ 1564202644 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/11 UVM_INFO @ 1564202644 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 2/11 UVM_INFO @ 2104377388 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 2/11 UVM_INFO @ 2104377388 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 3/11