Simulation Results: spi_host

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
99.29%
V2
99.04%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_host_smoke 120.000s 17124.741us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 18.976us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 122.569us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 105.451us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 43.888us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 43.676us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 122.569us 20 20 100.00
spi_host_csr_aliasing 2.000s 43.888us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 22.000s 34.601us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 12.000s 35.084us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 42.089us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 25.000s 2419.072us 50 50 100.00
spi_host_error_cmd 2.000s 71.701us 50 50 100.00
spi_host_event 599.000s 19163.055us 50 50 100.00
clock_rate 49 50 98.00
spi_host_speed 81.000s 10006.979us 49 50 98.00
speed 49 50 98.00
spi_host_speed 81.000s 10006.979us 49 50 98.00
chip_select_timing 49 50 98.00
spi_host_speed 81.000s 10006.979us 49 50 98.00
sw_reset 50 50 100.00
spi_host_sw_reset 100.000s 2923.951us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 82.587us 50 50 100.00
cpol_cpha 49 50 98.00
spi_host_speed 81.000s 10006.979us 49 50 98.00
full_cycle 49 50 98.00
spi_host_speed 81.000s 10006.979us 49 50 98.00
duplex 49 50 98.00
spi_host_smoke 120.000s 17124.741us 49 50 98.00
tx_rx_only 49 50 98.00
spi_host_smoke 120.000s 17124.741us 49 50 98.00
stress_all 48 50 96.00
spi_host_stress_all 1108.000s 1000000.000us 48 50 96.00
spien 48 50 96.00
spi_host_spien 113.000s 23600.446us 48 50 96.00
stall 50 50 100.00
spi_host_status_stall 118.000s 3216.287us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 12.000s 3186.563us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 25.000s 2419.072us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 14.543us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 29.000s 18.046us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 32.000s 316.585us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 32.000s 316.585us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 18.976us 5 5 100.00
spi_host_csr_rw 2.000s 122.569us 20 20 100.00
spi_host_csr_aliasing 2.000s 43.888us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 93.575us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 18.976us 5 5 100.00
spi_host_csr_rw 2.000s 122.569us 20 20 100.00
spi_host_csr_aliasing 2.000s 43.888us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 93.575us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 32.000s 516.592us 20 20 100.00
spi_host_sec_cm 2.000s 514.693us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 32.000s 516.592us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 556.000s 36315.632us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_speed 72820122811807929908426925784202988939718870354254268731543162944610625153805 199
UVM_FATAL @ 10006978946 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x26b30854, Comparison=CompareOpEq, exp_data=0x0, call_count=26
UVM_INFO @ 10006978946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:220) scoreboard [scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
spi_host_spien 36428923920931698559680202844009554696516350266615846398222817149863917306728 180
UVM_FATAL @ 1251820164 ps: (spi_host_scoreboard.sv:220) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
UVM_INFO @ 1251820164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 113262817996011661947443575437414289783338500404175959182992197194081810814998 308
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_smoke 18497820674051197219377626319094653634293302017541747211034325114159785160970 174
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 29974397595921136225101010348034300110095962213942086244712706776220281508279 163
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:439) scoreboard [scoreboard] CSB still low since last data sentThere's been * half SCK cycles (time, no ticks)
spi_host_spien 105854178342584480181748635233867091225291856423133173225398049410998317937291 325
UVM_FATAL @ 204317396 ps: (spi_host_scoreboard.sv:439) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] CSB still low since last data sentThere's been 18 half SCK cycles (time, no ticks)
UVM_INFO @ 204317396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---