Simulation Results: sram_ctrl

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.71 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.14 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.82%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 106.050s 463.172us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.080s 20.845us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.060s 16.964us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.040s 159.052us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.060s 11.109us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 9.020s 6918.821us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.060s 16.964us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 11.109us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 372.210s 74735.626us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 194.160s 87384.958us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1565.680s 105371.815us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 377.710s 5449.595us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2468.350s 1504742.544us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1447.280s 94362.951us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 141.320s 182831.433us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1377.260s 29465.695us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 107.050s 991.647us 50 50 100.00
sram_ctrl_partial_access_b2b 624.610s 53154.647us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 102.070s 785.798us 50 50 100.00
sram_ctrl_throughput_w_partial_write 108.050s 3264.077us 50 50 100.00
sram_ctrl_throughput_w_readback 126.350s 5352.755us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1107.470s 17077.508us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.540s 4799.029us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7456.480s 107233.969us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.060s 17.634us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.390s 126.850us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.390s 126.850us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 20.845us 5 5 100.00
sram_ctrl_csr_rw 1.060s 16.964us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 11.109us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 33.193us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.080s 20.845us 5 5 100.00
sram_ctrl_csr_rw 1.060s 16.964us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 11.109us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 33.193us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 64.930s 14760.707us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 3.560s 342.253us 20 20 100.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.560s 342.253us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1107.470s 17077.508us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1107.470s 17077.508us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.060s 16.964us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1377.260s 29465.695us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1377.260s 29465.695us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1377.260s 29465.695us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 141.320s 182831.433us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 41 50 82.00
sram_ctrl_mubi_enc_err 10.920s 13306.440us 41 50 82.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 64.930s 14760.707us 20 20 100.00
sec_cm_mem_readback 33 50 66.00
sram_ctrl_readback_err 12.950s 11004.976us 33 50 66.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 106.050s 463.172us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 106.050s 463.172us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1377.260s 29465.695us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 141.320s 182831.433us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 106.050s 463.172us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 29.491us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 164.030s 13072.216us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 67797267867450141851825635005720572783328637998969439401263009082919184533766 96
UVM_ERROR @ 29490623 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 29490623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 1415088493311001522250562168777503215340888527421892701844781169116209681208 96
UVM_ERROR @ 3379367 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3379367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 107646892231096444719301165176941486773108224943537462283466726100227491542296 96
UVM_ERROR @ 7312172 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7312172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 103887273125184328600874492646750516638454502786026888568604978466184664496119 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 741914255 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 741914255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 71574753631096335907346857521963385905983965123915222275150046029274639182782 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 665796562 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 665796562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 75598522831085574072285974808806207135370130648057865273741236588599673028089 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 717113077 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 717113077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 85824618011105747664970853115048491921357518673338016903722983034365905351391 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2784201557 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2784201557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 75601884786319198867687035582946029765079907359939037075895637862495625318360 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1392674726 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1392674726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 86550345953511939973268905346555264885873393418850003902802683232121093903210 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 13327416095 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 13327416095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 17947343486594489973438769987283833241071837413583312917472155197506217941497 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 667114792 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 667114792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 95134055469120908825505842917994937907847004169713112675762446290178276917213 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 673611261 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 673611261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 78825826994754422166360150363054264134352242415451624802343602298176480112056 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 985344263 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 985344263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 22670279623546848815582676866762277855495351652016277096879545361464504024106 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 7543215 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 7543215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 61644630260365318289325015166930677667149281696916111621200125981045519350590 95
UVM_ERROR @ 689501345 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x76)
UVM_INFO @ 689501345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 88008169859918184229103979182346697519066162182365013822751622577365820289618 95
UVM_ERROR @ 2628243871 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0x60)
UVM_INFO @ 2628243871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 72053908515094936880263386601541018488405901273767703540536656882797578720603 95
UVM_ERROR @ 662506441 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4f) != exp (0x26)
UVM_INFO @ 662506441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 17484343179022820385447299115767321753068043028140204610672618622865560498633 95
UVM_ERROR @ 662472527 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x37)
UVM_INFO @ 662472527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 78597987934086009976115438080232546373274433286630770461278689324342857426293 95
UVM_ERROR @ 1333744017 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x22)
UVM_INFO @ 1333744017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 98204524222452759927033502745540999248107497424593285349456126196830262310249 95
UVM_ERROR @ 2737287266 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x3b)
UVM_INFO @ 2737287266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 110400803058736855137333321767065741803523956733630635611355069425381665117724 95
UVM_ERROR @ 671560568 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x3a)
UVM_INFO @ 671560568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 33776697435058673613785363242647258928154621217352751680353266169546279569119 95
UVM_ERROR @ 686399959 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x31) != exp (0x59)
UVM_INFO @ 686399959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 108361747991509894199380152498946249808956134886723734617721300351854859538188 95
UVM_ERROR @ 7307148566 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x53) != exp (0x50)
UVM_INFO @ 7307148566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 50347798231658143354362165220351420732474168456813466996042432110741316817526 95
UVM_ERROR @ 1374463182 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x44) != exp (0x40)
UVM_INFO @ 1374463182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 110081552455121550193336255756322886255824523456155507567787558228709923718648 95
UVM_ERROR @ 11004975615 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x58) != exp (0x21)
UVM_INFO @ 11004975615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 8729003099725841010812685173902792139040953079966846329296821482563444308734 95
UVM_ERROR @ 1733550289 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x5e)
UVM_INFO @ 1733550289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 34635389771287320961992965233865363000770436465979641506824282974627977637487 95
UVM_ERROR @ 3458851772 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x45) != exp (0x36)
UVM_INFO @ 3458851772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 96667173813571755300133081068876315807665022646109414113666428043228270123861 95
UVM_ERROR @ 2742674720 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5b) != exp (0xe)
UVM_INFO @ 2742674720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 69381878174540225910684083916902984852905353086642577288741345259363735296450 95
UVM_ERROR @ 674005776 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x7c)
UVM_INFO @ 674005776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36976933475929919855794892308166757918845097267582511129634222781283329195757 95
UVM_ERROR @ 2630210138 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x56)
UVM_INFO @ 2630210138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 101569919217222191762782783380701944654662701123583415050698069528026497942988 95
UVM_ERROR @ 2054135391 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x13)
UVM_INFO @ 2054135391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 45991915584723924962158416488146457081221426533457814930439927794149617678193 98
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 2175676 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 2175676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---