Simulation Results: sram_ctrl

 
21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.14 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.57%
V2
100.00%
V2S
94.23%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 101.920s 620.200us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.040s 27.852us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.070s 25.427us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.420s 180.391us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.050s 34.620us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.970s 92.768us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.070s 25.427us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 34.620us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 14.570s 686.912us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 7.450s 671.659us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1257.770s 63781.251us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 430.400s 18523.592us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 108.350s 22943.241us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1112.980s 4713.516us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 12.060s 2302.764us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1341.350s 58178.438us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 107.840s 755.365us 50 50 100.00
sram_ctrl_partial_access_b2b 570.300s 145722.615us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 99.300s 1236.233us 50 50 100.00
sram_ctrl_throughput_w_partial_write 90.780s 147.757us 50 50 100.00
sram_ctrl_throughput_w_readback 109.240s 1041.282us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1515.100s 24593.989us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.210s 239.556us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5532.580s 81628.223us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.070s 14.331us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.090s 2220.760us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.090s 2220.760us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.040s 27.852us 5 5 100.00
sram_ctrl_csr_rw 1.070s 25.427us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 34.620us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 91.496us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.040s 27.852us 5 5 100.00
sram_ctrl_csr_rw 1.070s 25.427us 20 20 100.00
sram_ctrl_csr_aliasing 1.050s 34.620us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.210s 91.496us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.230s 792.709us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
sram_ctrl_tl_intg_err 3.190s 540.325us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.190s 540.325us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1515.100s 24593.989us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1515.100s 24593.989us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.070s 25.427us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1341.350s 58178.438us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1341.350s 58178.438us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1341.350s 58178.438us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 12.060s 2302.764us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 47 50 94.00
sram_ctrl_mubi_enc_err 2.180s 230.509us 47 50 94.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.230s 792.709us 20 20 100.00
sec_cm_mem_readback 38 50 76.00
sram_ctrl_readback_err 1.570s 234.534us 38 50 76.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 101.920s 620.200us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 101.920s 620.200us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1341.350s 58178.438us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 12.060s 2302.764us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 101.920s 620.200us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.200s 12.579us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
sram_ctrl_stress_all_with_rand_reset 796.540s 52342.351us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 40659837411912305774115365075139754089768979890413859577804669944034215894977 96
UVM_ERROR @ 8902028 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 8902028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 64295445457320114504278872168217109295376806048216574648985138386667245220400 98
UVM_ERROR @ 4363314 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4363314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 40456257492524904077040219967766783901052842177762953514420025873200222711295 102
UVM_ERROR @ 12579314 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 12579314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 58249261874445273781285774126459966369183805448446975015286036448052570221587 96
UVM_ERROR @ 2051002 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2051002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 12524702734233019985095679797384800763106981181114510043342853969908845919396 95
UVM_ERROR @ 23859858 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x34)
UVM_INFO @ 23859858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 95422278217756975673979729319846579807045356453495722835007702393119657760676 95
UVM_ERROR @ 46471526 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7b) != exp (0x27)
UVM_INFO @ 46471526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 19351936250280944782918056195451406410450780924619483143951289807968829792579 95
UVM_ERROR @ 125194330 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x23)
UVM_INFO @ 125194330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 34070397157469674818333258341705355558307310439516743958790176893272856918411 95
UVM_ERROR @ 47120079 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xf) != exp (0x31)
UVM_INFO @ 47120079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 17432924441803593999622755501596976203247359811836940469083548315408895409435 95
UVM_ERROR @ 24582648 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x44)
UVM_INFO @ 24582648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 51543151489619414404750628123157790367897434696553775096597601465472716990785 95
UVM_ERROR @ 94824719 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x2c)
UVM_INFO @ 94824719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 55010813613453712035680074731206791354344812835063013315516728257192365683297 95
UVM_ERROR @ 327696975 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x3f)
UVM_INFO @ 327696975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 81249837208688196931816541004407685398926894321066886043799160129318437519507 95
UVM_ERROR @ 88467709 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6a) != exp (0x76)
UVM_INFO @ 88467709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 4860658134941050155526791178881828033546446093132396188878732458551725781768 95
UVM_ERROR @ 24630520 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xe) != exp (0x43)
UVM_INFO @ 24630520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 15833563643169472780087465431594262366395832803525952236228263850346941123446 95
UVM_ERROR @ 27123965 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x50) != exp (0x6b)
UVM_INFO @ 27123965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 95549284528867050647337790942757766442037221966969948807352240809731054715876 95
UVM_ERROR @ 114893162 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x18)
UVM_INFO @ 114893162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 86158503035656577985110376108244418693557426409966512707945280532128480498753 100
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 34975151ps failed at 34975151ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 47020594 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 47020594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 39741952769774868214268721718123793354455362744040812208883989931629719319531 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 93742416 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 93742416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 112744680136391698637095264543393030475866157762219741188843896763407115599905 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 182202196 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 182202196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 109926462817532885684187172182415811715485649021545365396504134746011278868029 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 52705823 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 52705823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
sram_ctrl_stress_all_with_rand_reset 74298068923592761862974594526119854748087859200846982384788474725124906254550 243
UVM_ERROR @ 4846318020 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4846318020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5290) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_readback_err 15960754673453239587103156484456390720369210172341590926350119950510259510055 95
UVM_ERROR @ 234534484 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5290) { a_addr: 'h94ce73d0 a_data: 'h81 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hfb a_opcode: 'h0 a_user: 'h251ff d_param: 'h0 d_source: 'hfb d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 234534484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 90698541035402804841948872671512365083499027386704278038577409587012672297529 95
UVM_ERROR @ 47194919 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 47194919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---