sysrst_ctrl Simulation Results

Simulation Results: sysrst_ctrl

21/12/2025 00:05:28 sha: af01fe4 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.60 %

code
98.20 %

assert
98.37 %

func
93.22 %

line
99.00 %

branch
99.11 %

cond
98.04 %

toggle
100.00 %

FSM
94.87 %

Validation stages

V1		100.00%
V2		97.35%
V2S		100.00%
V3		94.00%

190/190 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sysrst_ctrl_smoke	8.820s	2116.986us	50	50	100.00
input_output_inverted				50	50	100.00
	sysrst_ctrl_in_out_inverted	10.330s	2474.035us	50	50	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	7.270s	2421.577us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.030s	2365.243us	5	5	100.00
csr_hw_reset				5	5	100.00
	sysrst_ctrl_csr_hw_reset	7.940s	6054.159us	5	5	100.00
csr_rw				20	20	100.00
	sysrst_ctrl_csr_rw	5.900s	2059.537us	20	20	100.00
csr_bit_bash				5	5	100.00
	sysrst_ctrl_csr_bit_bash	289.010s	75847.498us	5	5	100.00
csr_aliasing				5	5	100.00
	sysrst_ctrl_csr_aliasing	9.180s	3025.734us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.720s	2072.170us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sysrst_ctrl_csr_rw	5.900s	2059.537us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.180s	3025.734us	5	5	100.00

771/792 passed

97.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				49	50	98.00
	sysrst_ctrl_combo_detect	485.570s	195342.341us	49	50	98.00
combo_detect_with_pre_cond				95	100	95.00
	sysrst_ctrl_combo_detect_with_pre_cond	522.080s	256375.519us	95	100	95.00
auto_block_key_outputs				49	50	98.00
	sysrst_ctrl_auto_blk_key_output	637.240s	470240.165us	49	50	98.00
keyboard_input_triggered_interrupt				47	50	94.00
	sysrst_ctrl_edge_detect	731.590s	778630.281us	47	50	94.00
pin_output_keyboard_inversion_control				50	50	100.00
	sysrst_ctrl_pin_override_test	10.250s	2511.290us	50	50	100.00
pin_input_value_accessibility				50	50	100.00
	sysrst_ctrl_pin_access_test	9.150s	2243.453us	50	50	100.00
ec_power_on_reset				50	50	100.00
	sysrst_ctrl_ec_pwr_on_rst	2137.380s	891021.268us	50	50	100.00
flash_write_protect_output				50	50	100.00
	sysrst_ctrl_flash_wr_prot_out	10.640s	2610.497us	50	50	100.00
ultra_low_power_test				40	50	80.00
	sysrst_ctrl_ultra_low_pwr	230.010s	863604.841us	40	50	80.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	22.240s	40466.391us	2	2	100.00
stress_all				49	50	98.00
	sysrst_ctrl_stress_all	1282.920s	912902.460us	49	50	98.00
alert_test				50	50	100.00
	sysrst_ctrl_alert_test	8.310s	2013.290us	50	50	100.00
intr_test				50	50	100.00
	sysrst_ctrl_intr_test	6.300s	2010.994us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sysrst_ctrl_tl_errors	7.720s	2159.835us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sysrst_ctrl_tl_errors	7.720s	2159.835us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	7.940s	6054.159us	5	5	100.00
	sysrst_ctrl_csr_rw	5.900s	2059.537us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.180s	3025.734us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	25.020s	7303.893us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	7.940s	6054.159us	5	5	100.00
	sysrst_ctrl_csr_rw	5.900s	2059.537us	20	20	100.00
	sysrst_ctrl_csr_aliasing	9.180s	3025.734us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	25.020s	7303.893us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	sysrst_ctrl_tl_intg_err	118.480s	42486.511us	20	20	100.00
	sysrst_ctrl_sec_cm	133.310s	42010.650us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	sysrst_ctrl_tl_intg_err	118.480s	42486.511us	20	20	100.00

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				47	50	94.00
	sysrst_ctrl_stress_all_with_rand_reset	29.190s	148343.679us	47	50	94.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
	sysrst_ctrl_ultra_low_pwr	70832213336563626452297235742926399268489219743018022033885418266018945706507	648	UVM_ERROR @ 3048775105521 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 3048775355521 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3048775355521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all_with_rand_reset	70620965019752047231599170222426337311763656932282392181590873564219415763048	676	UVM_ERROR @ 58374850428 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 58374941338 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 58374941338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	83933309189785775265297841471218186541591288097355057096099702143455187413770	657	UVM_ERROR @ 2473421606 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 2473441606 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2473441606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	16307460606195941865060382154287276333354065678558385589250285983109645054684	649	UVM_ERROR @ 7403274266 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 7403315082 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 7403315082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	32736072474791982284785375287885909532879275841225153041401341059603349245373	648	UVM_ERROR @ 6579871538 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 6579891538 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 6579891538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	94574837422197577711932269982820171101511776341500585899289699396809622305135	647	UVM_ERROR @ 8178375521 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 8178455521 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 8178455521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	67402264766896646200631416098167191220986488048091113468169593838204673816343	663	UVM_ERROR @ 4638208414 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4638291748 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4638291748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	93293986483593424669925349847807973749776653214667341457858277302603588593888	649	UVM_ERROR @ 6223974842 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 6223994842 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 6223994842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	96514934827084482279641068847280165292061196777345143855157267983388438111863	653	UVM_ERROR @ 4696394172 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4696471096 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4696471096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	107941954224958100949252459757526859442108479584088662061445891283465927483312	648	UVM_ERROR @ 4894657290 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4894683264 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4894683264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	39457114355531791388916499182344702789871096171518477081720898466952809246211	647	UVM_ERROR @ 5437210276 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 5437290276 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5437290276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
	sysrst_ctrl_ultra_low_pwr	10019359388944080022732244601897540541125158138229429785087150248450308659401	647	UVM_ERROR @ 2205346655 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2402846655 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_ERROR @ 3883953238 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 3883953238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	94273746407817995595333033281393460114940478788395697310733108733114512458210	647	UVM_ERROR @ 2214888720 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2397388720 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_ERROR @ 3543676556 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 3543676556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	12527973485123290263446096698736301640752742367307018651767046287698837436411	647	UVM_ERROR @ 3075786275 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 3443286275 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 3443286275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	67102285056525802927045724246262655694133300807898369067165717097662778049049	647	UVM_ERROR @ 2218551144 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2256051144 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i UVM_INFO @ 4436051144 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 4448804946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	110966233160677806371734250617220588604676137823913706497469744017202170055337	690	UVM_ERROR @ 10135228826 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 10135228826 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (0 [0x0] vs 1 [0x1]) UVM_INFO @ 10135228826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [] vs [*])
	sysrst_ctrl_auto_blk_key_output	35194341086383214180448413460551473989886256595974636026812847662766457777893	649	UVM_ERROR @ 2544124455 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 2544124455 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2544124455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	65501090400076545349809590973664449205656847317752356862040627922222770722131	695	UVM_ERROR @ 62917787612 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 62932787612 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 62952787612 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_ERROR @ 63152836929 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (4 [0x4] vs 5 [0x5]) UVM_INFO @ 63152836929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
	sysrst_ctrl_combo_detect_with_pre_cond	100745876985847861287777092198038339870720794301391837243571719518322961600729	679	UVM_ERROR @ 37011998228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 37136998228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 37156998228 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 47306177465 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2d UVM_INFO @ 47306381545 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xb
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	85104425760227267531273227551710272334088525191178459133174099628705181240372	661	UVM_ERROR @ 16298364735 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4 UVM_ERROR @ 16298364735 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4 UVM_INFO @ 16298364735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	75933696583856648875509249778846913883392209990697013822441769697567912644537	670	UVM_ERROR @ 26442041234 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2]) UVM_ERROR @ 26442111234 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.intr_state reset value: 0x0 UVM_INFO @ 26442111234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	25833586776523100081540445135889197889736467705007546290094839360652764471552	716	UVM_ERROR @ 13289551062 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 13289551062 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:121) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_pwrb_in == inv_pwrb_out (0 [0x0] vs 1 [0x1]) UVM_INFO @ 13289551062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [] vs [*])
	sysrst_ctrl_combo_detect	5575278448415754596347364390712087700784457062470890228456832167054067656580	662	UVM_ERROR @ 56577911680 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1]) UVM_ERROR @ 56577959300 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.intr_state reset value: 0x0 UVM_INFO @ 56577959300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	98177729717849538739664550067827369710153665267905202951493015120601657813309	655	UVM_ERROR @ 14043752092 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 24329641152 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c UVM_INFO @ 24329682818 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1d UVM_INFO @ 24958752092 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0 UVM_INFO @ 24973752092 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 1e