Simulation Results: adc_ctrl

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.51 %
  • code
  • 98.74 %
  • assert
  • 95.95 %
  • func
  • 91.83 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 96.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.62%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 20.840s 5788.718us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 4.360s 988.537us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.540s 493.023us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 95.970s 51737.795us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 4.360s 845.851us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.150s 564.292us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.540s 493.023us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 845.851us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1154.970s 491543.213us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1080.950s 490647.698us 50 50 100.00
filters_interrupt 49 50 98.00
adc_ctrl_filters_interrupt 1257.230s 497265.399us 49 50 98.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1355.950s 497055.063us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1208.040s 537311.257us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1584.200s 615953.144us 50 50 100.00
filters_both 49 50 98.00
adc_ctrl_filters_both 1319.440s 594372.394us 49 50 98.00
clock_gating 32 50 64.00
adc_ctrl_clock_gating 1325.840s 599675.789us 32 50 64.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 18.380s 5192.629us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 127.220s 42293.818us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 380.940s 140405.006us 50 50 100.00
stress_all 50 50 100.00
adc_ctrl_stress_all 1043.000s 492258.046us 50 50 100.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.490s 494.152us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.390s 505.888us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.950s 530.573us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.950s 530.573us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 4.360s 988.537us 5 5 100.00
adc_ctrl_csr_rw 2.540s 493.023us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 845.851us 5 5 100.00
adc_ctrl_same_csr_outstanding 27.970s 4441.072us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 4.360s 988.537us 5 5 100.00
adc_ctrl_csr_rw 2.540s 493.023us 20 20 100.00
adc_ctrl_csr_aliasing 4.360s 845.851us 5 5 100.00
adc_ctrl_same_csr_outstanding 27.970s 4441.072us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 23.980s 8098.261us 5 5 100.00
adc_ctrl_tl_intg_err 30.220s 8503.025us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 30.220s 8503.025us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 45 50 90.00
adc_ctrl_stress_all_with_rand_reset 480.380s 10000000.000us 45 50 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_stress_all_with_rand_reset 47629434302934061847404119889333709818438784565830982148830803831679609047481 402
UVM_ERROR @ 14177103410 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 14177103410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 76968116935700871493780046497220332781046203436522104957957744727337462841886 318
UVM_ERROR @ 7277231071 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 7277231071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 103282851038413439290064507726807600732111608285805347003817031468863702201218 352
UVM_ERROR @ 335407485135 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 335407485135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 77100666952098682383136212823725528257472703879047222452848506088948633343358 318
UVM_ERROR @ 1724841657 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1724841657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 14609574218459710526266536901557118089306146877385985136101181636933697858337 335
UVM_ERROR @ 173667130295 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 173667130295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 523986831737038510591754119919962247056523648876182156074715289264680966003 335
UVM_ERROR @ 183617375594 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 183617375594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 99307114760637993986205363188676402945396680406233820174528958623432105400729 335
UVM_ERROR @ 187687077383 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 187687077383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 6737395363507073772469263956629685052811583701624568311513833412894440300573 331
UVM_ERROR @ 3606545550 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3606545550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 82459675202369986893100043085292527467007832024629209907162186552787482945156 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 52330242925452597198060417584963825276259237992884692766671166877648028170544 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 49073250880945283517019169234632755705593155144270492528356167622547791904138 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 36118028783736063905421517934177106723228890906094917623862907514316397065495 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 88972142619064664152470726351918738504973535918932939188503984857594650248119 344
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 46383488080931519193750442400221097940188892655124769754701171582808324205870 401
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 97970691077249616118065237801251467818154703713042749706686742619083461852280 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 26386239420997489046244071599523771979881438300758012468489040150707514302794 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 107005716860038203628199871101287987326379358300473577024288891532398257826353 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 74647584937232710975011854902410917452930179200953605371930019803080610281145 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 7626734680575910182617581041892400442570170452328811795916235270086144446339 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 90471910812880737666679037163051509876637847816969416047347160712714440295782 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 90137866757915331962648677324490254954195807865498130234515550466978617391965 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 105492237240293293420559373012338526102610076393725884446973427738691209847883 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_filters_interrupt 61749725175134101816402401784099355234013725495919788216789791062467656948101 318
UVM_ERROR @ 163073088415 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 163073088415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 79440273457604262251034572105435929689159504988247798633140512067757999734174 318
UVM_ERROR @ 81107371022 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 81107371022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(np_sample_cnt_q == '0)'
adc_ctrl_stress_all_with_rand_reset 104842393161641662107678115868595339639483449566603739502077572133413771034920 460
Offending '(np_sample_cnt_q == '0)'
UVM_ERROR @ 40954031632 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 40954031632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---