clkmgr Simulation Results

Simulation Results: clkmgr

28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
98.95 %

assert
96.47 %

func
87.82 %

line
99.34 %

branch
99.17 %

cond
96.26 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		98.29%
V3		99.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	1.620s	357.810us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	1.190s	81.340us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	8.450s	2083.302us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	1.470s	141.035us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.500s	38.558us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
	clkmgr_csr_aliasing	1.470s	141.035us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.080s	113.210us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.200s	196.141us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	1.310s	280.475us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	0.990s	18.224us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	1.620s	357.810us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	10.590s	2243.870us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	10.160s	2420.235us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	10.590s	2243.870us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	88.240s	16518.383us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.010s	69.550us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	4.270s	1205.691us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	4.270s	1205.691us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	1.190s	81.340us	5	5	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
	clkmgr_csr_aliasing	1.470s	141.035us	5	5	100.00
	clkmgr_same_csr_outstanding	2.080s	653.422us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	1.190s	81.340us	5	5	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
	clkmgr_csr_aliasing	1.470s	141.035us	5	5	100.00
	clkmgr_same_csr_outstanding	2.080s	653.422us	20	20	100.00

V2S

575/585 passed

98.29 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				22	25	88.00
	clkmgr_sec_cm	2.340s	427.133us	2	5	40.00
	clkmgr_tl_intg_err	4.150s	1360.995us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.450s	709.267us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	2.450s	709.267us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.450s	709.267us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	2.450s	709.267us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	3.160s	394.111us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	4.150s	1360.995us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	10.590s	2243.870us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	10.160s	2420.235us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	2.450s	709.267us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	1.480s	354.192us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.360s	262.732us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.370s	265.387us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				49	50	98.00
	clkmgr_clk_handshake_intersig_mubi	1.660s	474.987us	49	50	98.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.140s	78.740us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	2.340s	427.133us	2	5	40.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	0.950s	20.224us	20	20	100.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	2.340s	427.133us	2	5	40.00

99/100 passed

99.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	4.460s	1112.915us	50	50	100.00
stress_all_with_rand_reset				49	50	98.00
	clkmgr_stress_all_with_rand_reset	136.210s	44864.163us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	62910536182292435259662488427206748264145926863977309450802406720652210974462	79	UVM_ERROR @ 7731032 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 7731032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	33769475584511835506083661171688610196416943114094156174765527736804170272782	74	UVM_ERROR @ 2305628 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 2305628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	109308377444132069521695746675239377226740199881293592243778264364797103147594	89	UVM_ERROR @ 139479999 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 139479999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(lc_clk_byp_req \|\| (io_clk_byp_req_o != MuBi4False))'
	clkmgr_stress_all_with_rand_reset	51308854268010052820812203900287364016952214399265445939337804413178413496172	119	Offending '(lc_clk_byp_req \|\| (io_clk_byp_req_o != MuBi4False))' UVM_ERROR @ 157368774 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A UVM_INFO @ 157368774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	89973738814591856250909803520008927000831060826950405963955603526840250368573	71	UVM_ERROR @ 9204347 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (3 [0x3] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 9204347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---