Simulation Results: csrng

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.47 %
  • code
  • 96.35 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.76 %
  • line
  • 99.64 %
  • branch
  • 96.88 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.81%
V2S
99.94%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 4.000s 67.212us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 74.379us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 20.745us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 20.000s 941.323us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 4.000s 67.824us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 90.284us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 20.745us 20 20 100.00
csrng_csr_aliasing 4.000s 67.824us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
alerts 500 500 100.00
csrng_alert 41.000s 3209.613us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 132.073us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 376.000s 38191.189us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 376.000s 38191.189us 50 50 100.00
stress_all 47 50 94.00
csrng_stress_all 917.000s 44663.682us 47 50 94.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 77.316us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 7.000s 177.509us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 7.000s 127.910us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 7.000s 127.910us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 74.379us 5 5 100.00
csrng_csr_rw 3.000s 20.745us 20 20 100.00
csrng_csr_aliasing 4.000s 67.824us 5 5 100.00
csrng_same_csr_outstanding 6.000s 327.990us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 74.379us 5 5 100.00
csrng_csr_rw 3.000s 20.745us 20 20 100.00
csrng_csr_aliasing 4.000s 67.824us 5 5 100.00
csrng_same_csr_outstanding 6.000s 327.990us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
csrng_tl_intg_err 12.000s 419.854us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 3.000s 90.716us 50 50 100.00
csrng_csr_rw 3.000s 20.745us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 41.000s 3209.613us 500 500 100.00
sec_cm_intersig_mubi 47 50 94.00
csrng_stress_all 917.000s 44663.682us 47 50 94.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 41.000s 3209.613us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
sec_cm_constants_lc_gated 47 50 94.00
csrng_stress_all 917.000s 44663.682us 47 50 94.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 41.000s 3209.613us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 12.000s 419.854us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
csrng_sec_cm 5.000s 126.257us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 21.000s 1402.189us 200 200 100.00
csrng_err 4.000s 132.073us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 373.000s 24657.500us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 65618340561214715284788015882268743745662927211043190988300926404960399591875 156
UVM_ERROR @ 19635895029 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 19635895029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 27807732623306718519955479630955756548738058165527445513969592341131360873892 146
UVM_ERROR @ 1085314821 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1085314821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 69565291196977316409333822816761103027433949561601772738954267680134787656867 149
UVM_ERROR @ 2756149209 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 2756149209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---