flash_ctrl Simulation Results

Simulation Results: flash_ctrl

28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.90 %

code
95.63 %

assert
96.71 %

func
98.36 %

line
96.08 %

branch
97.41 %

cond
94.85 %

toggle
98.66 %

FSM
91.16 %

Validation stages

V1		100.00%
V2		99.12%
V2S		99.27%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	169.440s	149.395us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	19.650s	29.587us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	40.490s	43.616us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	77.310s	4455.430us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	70.320s	6808.349us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	17.190s	108.397us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
	flash_ctrl_csr_aliasing	70.320s	6808.349us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	11.590s	39.153us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	11.500s	55.623us	5	5	100.00

1126/1136 passed

99.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	23.030s	27.724us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	52.160s	110.790us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1687.760s	337784.790us	3	3	100.00
	flash_ctrl_hw_rma_reset	801.340s	420343.094us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.420s	42.546us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2177.010s	264331.391us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	366.160s	4662.420us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	185.990s	2574.861us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3208.100s	50873.175us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	223.440s	4178.778us	5	5	100.00
rd_buff_eviction_w_ecc				95	100	95.00
	flash_ctrl_rw_evict	31.660s	40.389us	37	40	92.50
	flash_ctrl_rw_evict_all_en	31.370s	159.038us	38	40	95.00
	flash_ctrl_re_evict	33.480s	181.404us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	264.030s	2798.656us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	264.030s	2798.656us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	917.890s	118399.286us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	25.700s	298.175us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	664.570s	2767.451us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	698.770s	4216.464us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	599.820s	665.802us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1386.070s	2055.645us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.540s	24.016us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	163.970s	1503.703us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	21.940s	46.893us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.240s	56.691us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	1093.320s	843.197us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	186.860s	32495.649us	50	50	100.00
	flash_ctrl_otp_reset	119.330s	83.409us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1687.760s	337784.790us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	166.350s	6556.795us	38	40	95.00
	flash_ctrl_intr_wr	78.700s	5530.077us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	380.190s	51184.408us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	317.430s	44109.748us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	74.840s	6189.819us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	73.420s	1711.304us	5	5	100.00
double_bit_err				35	35	100.00
	flash_ctrl_read_word_sweep_derr	21.390s	120.873us	5	5	100.00
	flash_ctrl_ro_derr	154.430s	1580.986us	10	10	100.00
	flash_ctrl_rw_derr	211.490s	6336.722us	10	10	100.00
	flash_ctrl_derr_detect	167.000s	983.169us	5	5	100.00
	flash_ctrl_integrity	440.060s	10540.026us	5	5	100.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	20.450s	40.407us	5	5	100.00
	flash_ctrl_ro_serr	135.860s	12965.699us	10	10	100.00
	flash_ctrl_rw_serr	206.970s	35067.471us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	107.880s	1160.378us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	108.490s	1294.543us	5	5	100.00
scramble				60	62	96.77
	flash_ctrl_wo	288.160s	13215.991us	20	20	100.00
	flash_ctrl_write_word_sweep	8.700s	40.919us	1	1	100.00
	flash_ctrl_read_word_sweep	9.520s	70.750us	1	1	100.00
	flash_ctrl_ro	115.650s	1275.741us	20	20	100.00
	flash_ctrl_rw	505.930s	10092.355us	18	20	90.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	35.820s	1038.389us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	775.410s	91503.109us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	280.040s	10020.125us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.680s	129.248us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	11.770s	23.939us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	18.750s	71.130us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	18.750s	71.130us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	40.490s	43.616us	5	5	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
	flash_ctrl_csr_aliasing	70.320s	6808.349us	5	5	100.00
	flash_ctrl_same_csr_outstanding	28.140s	165.846us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	40.490s	43.616us	5	5	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
	flash_ctrl_csr_aliasing	70.320s	6808.349us	5	5	100.00
	flash_ctrl_same_csr_outstanding	28.140s	165.846us	20	20	100.00

V2S

817/823 passed

99.27 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	92.220s	108.438us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	544.800s	879.602us	20	20	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	544.800s	879.602us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	544.800s	879.602us	20	20	100.00
sec_cm_mem_bus_integrity				5	6	83.33
	flash_ctrl_rd_intg	25.610s	64.289us	3	3	100.00
	flash_ctrl_wr_intg	12.940s	46.402us	2	3	66.67
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	169.440s	149.395us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	119.330s	83.409us	80	80	100.00
	flash_ctrl_disable	21.940s	46.893us	50	50	100.00
	flash_ctrl_sec_info_access	72.810s	23678.492us	50	50	100.00
	flash_ctrl_connect	17.240s	56.691us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	11.040s	51.786us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.570s	423.544us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	84.080s	313.037us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	21.940s	46.893us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	25.610s	64.289us	3	3	100.00
	flash_ctrl_access_after_disable	11.580s	20.930us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	27.990s	39.506us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	21.940s	46.893us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	25.700s	298.175us	10	10	100.00
sec_cm_mem_scramble				18	20	90.00
	flash_ctrl_rw	505.930s	10092.355us	18	20	90.00
sec_cm_mem_integrity				25	25	100.00
	flash_ctrl_rw_serr	206.970s	35067.471us	10	10	100.00
	flash_ctrl_rw_derr	211.490s	6336.722us	10	10	100.00
	flash_ctrl_integrity	440.060s	10540.026us	5	5	100.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1687.760s	337784.790us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	22.840s	803.268us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				2	5	40.00
	flash_ctrl_phy_host_grant_err	13.340s	23.326us	2	5	40.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	11.960s	23.268us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2214.060s	2104.328us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	31.840s	78.242us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	437.600s	1197.077us	3	3	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp f061c572_182eefd6:ffffffff_182eefd mismatch!!
	flash_ctrl_intr_rd	107987687608280156751778805857922805966492315115555728531744338664815092366233	105	UVM_ERROR @ 4899279.9 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 3: obs:exp f061c572_182eefd6:ffffffff_182eefd6 mismatch!! UVM_INFO @ 4899279.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	flash_ctrl_rw	87943811706865254335478654603904583328392873083379475859945217233246075879856	None	Job timed out after 60 minutes
	flash_ctrl_prog_reset	62267859851032788000441585357297192398167511763664897670294145341431673631823	None	Job timed out after 60 minutes
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
	flash_ctrl_phy_host_grant_err	58548590237289985647542859667026575359271717331927732641087658233888431025961	122	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 5201.3 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 5201.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	100266009092234807339049190883767493430917255987436045649212286318115334831212	122	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 5150.5 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 5150.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_phy_host_grant_err	102608891321801290329100609747818954459111003214761020206248431524146825023987	122	Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' UVM_ERROR @ 95780.2 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 95780.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank1] : obs:exp ff__bcf192f0_2bd66d8f:__a3da4089_7eb2e* mismatch!!
	flash_ctrl_wr_intg	13048106201447618704454429076958398830276860106708243882622941968070230280704	122	UVM_ERROR @ 45181.6 ns: (flash_ctrl_otf_scoreboard.sv:368) [wdata_page0_comp_bank1] 0: obs:exp ff_9_bcf192f0_2bd66d8f:70_9_a3da4089_7eb2e364 mismatch!! UVM_INFO @ 45181.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict_all_en	105737820890037345178348817489642989718995384241431052499254054600452782978242	105	UVM_ERROR @ 11879.1 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 11879.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	62843238255403584920902928865844927126990732363228169611786113766912912581327	105	UVM_ERROR @ 9228.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 9228.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	54710442266262630013505298088139692254802303387439787275513165934281164915695	105	UVM_ERROR @ 10001.1 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 10001.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	10176401759224663660597466176527955499883835451144771444961363113171214590890	105	UVM_ERROR @ 41123.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 41123.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	77667683495156840904874121033375004423234766555648231285973931578693916343669	105	UVM_ERROR @ 11469.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 11469.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp a0b3190d_307a4cc0:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	23881919310578893578978897881093327315538231285524119748738427753091082371566	105	UVM_ERROR @ 11447853.1 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 7: obs:exp a0b3190d_307a4cc0:ffffffff_ffffffff mismatch!! UVM_INFO @ 11447853.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_err triggered unexpectedly
	flash_ctrl_rw	54976962819723649847156370771403609400712406163031140858332770554363851903152	105	UVM_ERROR @ 8776747.4 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly UVM_INFO @ 8776747.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---