Simulation Results: hmac

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.79 %
  • code
  • 98.75 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.91 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.270s 5119.738us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.250s 132.090us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.250s 137.227us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 13.610s 310.974us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 5.990s 1197.412us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 729.850s 864002.821us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.250s 137.227us 20 20 100.00
hmac_csr_aliasing 5.990s 1197.412us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 73.460s 19302.394us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 78.930s 31278.875us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 240.940s 12249.041us 30 30 100.00
hmac_test_sha384_vectors 546.030s 150492.827us 75 75 100.00
hmac_test_sha512_vectors 526.250s 14380.317us 75 75 100.00
hmac_test_hmac256_vectors 13.690s 2379.687us 50 50 100.00
hmac_test_hmac384_vectors 15.740s 1606.418us 60 60 100.00
hmac_test_hmac512_vectors 17.430s 473.937us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 40.210s 6950.609us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1256.840s 7197.251us 10 10 100.00
error 10 10 100.00
hmac_error 90.090s 15342.593us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 122.140s 43172.382us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.270s 5119.738us 10 10 100.00
hmac_long_msg 73.460s 19302.394us 10 10 100.00
hmac_back_pressure 78.930s 31278.875us 25 25 100.00
hmac_datapath_stress 1256.840s 7197.251us 10 10 100.00
hmac_burst_wr 40.210s 6950.609us 50 50 100.00
hmac_stress_all 1833.410s 50473.936us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.270s 5119.738us 10 10 100.00
hmac_long_msg 73.460s 19302.394us 10 10 100.00
hmac_back_pressure 78.930s 31278.875us 25 25 100.00
hmac_datapath_stress 1256.840s 7197.251us 10 10 100.00
hmac_wipe_secret 122.140s 43172.382us 10 10 100.00
hmac_test_sha256_vectors 240.940s 12249.041us 30 30 100.00
hmac_test_sha384_vectors 546.030s 150492.827us 75 75 100.00
hmac_test_sha512_vectors 526.250s 14380.317us 75 75 100.00
hmac_test_hmac256_vectors 13.690s 2379.687us 50 50 100.00
hmac_test_hmac384_vectors 15.740s 1606.418us 60 60 100.00
hmac_test_hmac512_vectors 17.430s 473.937us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.270s 5119.738us 10 10 100.00
hmac_long_msg 73.460s 19302.394us 10 10 100.00
hmac_back_pressure 78.930s 31278.875us 25 25 100.00
hmac_datapath_stress 1256.840s 7197.251us 10 10 100.00
hmac_burst_wr 40.210s 6950.609us 50 50 100.00
hmac_error 90.090s 15342.593us 10 10 100.00
hmac_wipe_secret 122.140s 43172.382us 10 10 100.00
hmac_test_sha256_vectors 240.940s 12249.041us 30 30 100.00
hmac_test_sha384_vectors 546.030s 150492.827us 75 75 100.00
hmac_test_sha512_vectors 526.250s 14380.317us 75 75 100.00
hmac_test_hmac256_vectors 13.690s 2379.687us 50 50 100.00
hmac_test_hmac384_vectors 15.740s 1606.418us 60 60 100.00
hmac_test_hmac512_vectors 17.430s 473.937us 75 75 100.00
hmac_stress_all 1833.410s 50473.936us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1833.410s 50473.936us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.940s 15.592us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.980s 16.462us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.030s 237.349us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.030s 237.349us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.250s 132.090us 5 5 100.00
hmac_csr_rw 1.250s 137.227us 20 20 100.00
hmac_csr_aliasing 5.990s 1197.412us 5 5 100.00
hmac_same_csr_outstanding 2.990s 144.125us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.250s 132.090us 5 5 100.00
hmac_csr_rw 1.250s 137.227us 20 20 100.00
hmac_csr_aliasing 5.990s 1197.412us 5 5 100.00
hmac_same_csr_outstanding 2.990s 144.125us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.360s 128.013us 5 5 100.00
hmac_tl_intg_err 5.020s 284.601us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 5.020s 284.601us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.270s 5119.738us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.280s 1641.751us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 488.950s 6089.436us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.960s 568.661us 1 1 100.00

Error Messages

   Test seed line log context