keymgr Simulation Results

Simulation Results: keymgr

28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.92 %

code
98.92 %

assert
97.72 %

func
91.11 %

line
99.13 %

branch
99.01 %

cond
98.22 %

toggle
98.26 %

FSM
100.00 %

Validation stages

V1		98.89%
V2		98.81%
V2S		99.03%
V3		56.00%

178/180 passed

98.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	13.940s	1102.660us	50	50	100.00
random				50	50	100.00
	keymgr_random	54.950s	7971.702us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	1.020s	211.068us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	16.740s	861.901us	5	5	100.00
csr_aliasing				4	5	80.00
	keymgr_csr_aliasing	5.980s	537.499us	4	5	80.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	1.860s	64.307us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				24	25	96.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_csr_aliasing	5.980s	537.499us	4	5	80.00

830/840 passed

98.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				50	50	100.00
	keymgr_cfg_regwen	75.040s	10435.177us	50	50	100.00
sideload				200	200	100.00
	keymgr_sideload	27.630s	1681.281us	50	50	100.00
	keymgr_sideload_kmac	41.720s	5991.774us	50	50	100.00
	keymgr_sideload_aes	32.390s	1373.770us	50	50	100.00
	keymgr_sideload_otbn	33.110s	8215.510us	50	50	100.00
direct_to_disabled_state				50	50	100.00
	keymgr_direct_to_disabled	26.830s	4317.388us	50	50	100.00
lc_disable				46	50	92.00
	keymgr_lc_disable	13.400s	687.123us	46	50	92.00
kmac_error_response				49	50	98.00
	keymgr_kmac_rsp_err	10.060s	1439.951us	49	50	98.00
invalid_sw_input				50	50	100.00
	keymgr_sw_invalid_input	28.490s	5485.587us	50	50	100.00
invalid_hw_input				49	50	98.00
	keymgr_hwsw_invalid_input	16.340s	3569.278us	49	50	98.00
sync_async_fault_cross				50	50	100.00
	keymgr_sync_async_fault_cross	4.610s	3672.450us	50	50	100.00
stress_all				48	50	96.00
	keymgr_stress_all	160.550s	48398.923us	48	50	96.00
intr_test				50	50	100.00
	keymgr_intr_test	0.980s	13.479us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.220s	63.898us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	4.200s	154.605us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	4.200s	154.605us	20	20	100.00
tl_d_outstanding_access				49	50	98.00
	keymgr_csr_hw_reset	1.020s	211.068us	5	5	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_csr_aliasing	5.980s	537.499us	4	5	80.00
	keymgr_same_csr_outstanding	3.190s	114.208us	20	20	100.00
tl_d_partial_access				49	50	98.00
	keymgr_csr_hw_reset	1.020s	211.068us	5	5	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_csr_aliasing	5.980s	537.499us	4	5	80.00
	keymgr_same_csr_outstanding	3.190s	114.208us	20	20	100.00

V2S

1020/1030 passed

99.03 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_tl_intg_err	5.990s	220.578us	20	20	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	4.490s	255.127us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	4.490s	255.127us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	4.490s	255.127us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	4.490s	255.127us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	11.880s	2347.897us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	5.990s	220.578us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	4.490s	255.127us	20	20	100.00
sec_cm_op_config_regwen				50	50	100.00
	keymgr_cfg_regwen	75.040s	10435.177us	50	50	100.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_random	54.950s	7971.702us	50	50	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_random	54.950s	7971.702us	50	50	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_csr_rw	1.230s	26.451us	20	20	100.00
	keymgr_random	54.950s	7971.702us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				46	50	92.00
	keymgr_lc_disable	13.400s	687.123us	46	50	92.00
sec_cm_constants_consistency				49	50	98.00
	keymgr_hwsw_invalid_input	16.340s	3569.278us	49	50	98.00
sec_cm_intersig_consistency				49	50	98.00
	keymgr_hwsw_invalid_input	16.340s	3569.278us	49	50	98.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	54.950s	7971.702us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	17.900s	3191.295us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_ctrl_fsm_consistency				50	50	100.00
	keymgr_custom_cm	11.700s	943.228us	50	50	100.00
sec_cm_ctrl_fsm_global_esc				46	50	92.00
	keymgr_lc_disable	13.400s	687.123us	46	50	92.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	11.700s	943.228us	50	50	100.00
sec_cm_kmac_if_done_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	11.700s	943.228us	50	50	100.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				50	50	100.00
	keymgr_custom_cm	11.700s	943.228us	50	50	100.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	9.880s	2371.325us	5	5	100.00
sec_cm_ctrl_key_integrity				50	50	100.00
	keymgr_custom_cm	11.700s	943.228us	50	50	100.00

28/50 passed

56.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				28	50	56.00
	keymgr_stress_all_with_rand_reset	23.710s	10260.867us	28	50	56.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: keymgr_reg_block.err_code reset value:
	keymgr_csr_aliasing	102475386204063998389530060308526260017965657134127437217264427515024972103764	78	UVM_ERROR @ 182819268 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 0 [0x0]) Regname: keymgr_reg_block.err_code reset value: 0x0 UVM_INFO @ 182819268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	keymgr_stress_all_with_rand_reset	110499508574364178401633295914513517484914847472649372831476381184051630328722	1655	UVM_ERROR @ 1074142840 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1074142840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	56889540245144543269766002213370775360170367343392176278215783940019022034647	411	UVM_ERROR @ 145302597 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 145302597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	28424729215918452658721599067976623193406222278188818311446571291479000291783	408	UVM_ERROR @ 314801208 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 314801208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	75804231490030018300883150197715337212333508797527876470800096077567412524741	338	UVM_ERROR @ 161171530 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 161171530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	16598870007110986885838858315326260013450059676101694928770826737746109655714	153	UVM_ERROR @ 455496365 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 455496365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	74059830832486003202647698871156485173449115580667071665985248272897170385923	310	UVM_ERROR @ 265442049 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 265442049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	27949472711928213015883170885082412509897074510544635333690010624353896511453	161	UVM_ERROR @ 319141071 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 319141071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	79186745741941515918603271726298737876138696310529271015837746971912244419643	227	UVM_ERROR @ 777205089 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 777205089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	43049136031935834068796711689997756085222383944032515657840409377546487595378	522	UVM_ERROR @ 667351429 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 667351429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	49447550203329409301035281172795258625562174385773409517958664738658620501124	751	UVM_ERROR @ 1357239117 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1357239117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	29879595561967683008128921652487850548164563570681502752565905190088366764580	1120	UVM_ERROR @ 743641318 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 743641318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	78476794117518435317590801458022578120759673915496618082603813643742115984597	1411	UVM_ERROR @ 8678919149 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 8678919149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	106396194158747398597580419669663771217135818233271702867715942391144947545814	584	UVM_ERROR @ 406310533 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 406310533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	29710894335519160188379080279537783120695355280926585561645617579478446251974	455	UVM_ERROR @ 902673431 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 902673431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	40191548753926705370242379029228943046390354070812997835363837704751955097582	884	UVM_ERROR @ 964994777 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 964994777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	102454946052639175790509143693950163603131319099275310218118047434168533346155	745	UVM_ERROR @ 1390496604 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1390496604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	20351884611759682817587875880464278121777236495235623181010722942327355637527	422	UVM_ERROR @ 616660651 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 616660651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	14374181420121288015855306136611892475137840886077478110141430890762936237247	125	UVM_ERROR @ 773144571 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 773144571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	68869138367587981500996186977247634994414266814539077695490194027333749225324	1117	UVM_ERROR @ 1922167692 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1922167692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	33148402227508603420567536273009156778839381066820483463571828532500775414649	731	UVM_ERROR @ 245516115 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 245516115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [] vs [*])
	keymgr_stress_all_with_rand_reset	14404039648529625263702059102094103680706245569840522902023154565413985581553	277	UVM_ERROR @ 361818250 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2]) UVM_INFO @ 361818250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
	keymgr_lc_disable	49197115098592227109294843656732987367861402960139050491917571792019854792895	194	UVM_ERROR @ 62954731 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 62954731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_kmac_rsp_err	26667803020537656561591071323223080036556051167067827152848402607410842253526	112	UVM_ERROR @ 16042325 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 16042325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_hwsw_invalid_input	64848747301376361485021315059935329997784318947575985523599468621380554899592	329	UVM_ERROR @ 40169912 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4 UVM_INFO @ 40169912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) KMAC key at state StCreatorRootKey for Sealing Kmac
	keymgr_stress_all	50126959008654935042074933819032855820122340537176185736423234773513320152952	1233	UVM_ERROR @ 619872794 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (7429496735122883132241891885096330098654876442490191713232280208965527248100202424556568037236386958105556763833677127855413785010545668470963253567976205 [0x8dda9fa30ea556aa9908b39b496f2b4a85c6ca9ba1e7b46ca98b315ebbc430594843aa8cf61c5d39911ab47617f5a66797db44e61905a6b72aa06c6824be730d] vs 7429496735122883132241891885096330098654876442490191713232280208965527248100202424556568037236386958105556763833677127855413785010545668470963253567976205 [0x8dda9fa30ea556aa9908b39b496f2b4a85c6ca9ba1e7b46ca98b315ebbc430594843aa8cf61c5d39911ab47617f5a66797db44e61905a6b72aa06c6824be730d]) KMAC key at state StCreatorRootKey for Sealing Kmac UVM_INFO @ 619872794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share1_output_
	keymgr_lc_disable	79508873936450894554431189286386094884550992815442122652295400847874644837241	95	UVM_ERROR @ 12475581 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4 UVM_INFO @ 12475581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_lc_disable	8139437156746756226681624116920985143664803352346168892017079320980936712700	279	UVM_ERROR @ 66622698 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_6 UVM_INFO @ 66622698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_lc_disable	89288741758782221960251773668167286073660665227948481969723839047761011403563	198	UVM_ERROR @ 190907903 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3452651612 [0xcdcb485c] vs 3452651612 [0xcdcb485c]) reg name: keymgr_reg_block.sw_share1_output_0 UVM_INFO @ 190907903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [] vs [*])
	keymgr_stress_all	53858220897940584549922677028618562016253824462143000949245485945524452252242	4041	UVM_ERROR @ 3439017849 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (4 [0x4] vs 6 [0x6]) UVM_INFO @ 3439017849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	keymgr_stress_all_with_rand_reset	28070457129875678160048427616460516941058789167836668385229112338578900043495	103	UVM_ERROR @ 441162042 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 441162042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---