Simulation Results: kmac

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.58 %
  • code
  • 94.04 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.76 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
99.88%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 101.930s 4337.843us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.520s 43.492us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.510s 128.056us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.260s 1455.084us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.850s 560.858us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.620s 289.215us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.510s 128.056us 20 20 100.00
kmac_csr_aliasing 7.850s 560.858us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.120s 12.026us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.900s 181.824us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3348.660s 85292.962us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1513.280s 280900.502us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2498.140s 374838.579us 5 5 100.00
kmac_test_vectors_sha3_256 2534.150s 340029.172us 5 5 100.00
kmac_test_vectors_sha3_384 1756.770s 1115637.389us 5 5 100.00
kmac_test_vectors_sha3_512 1457.710s 273272.064us 5 5 100.00
kmac_test_vectors_shake_128 1820.030s 161856.780us 5 5 100.00
kmac_test_vectors_shake_256 2008.280s 227064.956us 5 5 100.00
kmac_test_vectors_kmac 3.850s 328.038us 5 5 100.00
kmac_test_vectors_kmac_xof 4.030s 361.980us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 636.520s 271808.703us 50 50 100.00
app 50 50 100.00
kmac_app 573.610s 379573.011us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 347.860s 16003.481us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 483.870s 78944.779us 50 50 100.00
error 50 50 100.00
kmac_error 517.430s 27772.032us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 19.850s 7482.883us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.000s 5329.859us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 49.720s 2254.248us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.570s 5335.035us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 91.250s 32830.941us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 36.400s 1365.419us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3148.860s 1455633.821us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 39.149us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.310s 78.137us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.940s 1846.366us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.940s 1846.366us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.520s 43.492us 5 5 100.00
kmac_csr_rw 1.510s 128.056us 20 20 100.00
kmac_csr_aliasing 7.850s 560.858us 5 5 100.00
kmac_same_csr_outstanding 3.010s 98.655us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.520s 43.492us 5 5 100.00
kmac_csr_rw 1.510s 128.056us 20 20 100.00
kmac_csr_aliasing 7.850s 560.858us 5 5 100.00
kmac_same_csr_outstanding 3.010s 98.655us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.400s 241.026us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.400s 241.026us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.400s 241.026us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.400s 241.026us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.650s 4278.595us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.780s 248.082us 20 20 100.00
kmac_sec_cm 113.700s 13938.411us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.780s 248.082us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 36.400s 1365.419us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 101.930s 4337.843us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 636.520s 271808.703us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.400s 241.026us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 113.700s 13938.411us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 113.700s 13938.411us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 113.700s 13938.411us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 101.930s 4337.843us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 36.400s 1365.419us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 113.700s 13938.411us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 378.010s 67241.065us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 101.930s 4337.843us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
kmac_stress_all_with_rand_reset 219.990s 12259.123us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 72968172403497982078965726190861889809018232643032871551507383866284525611775 227
UVM_ERROR @ 1354045620 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1354045620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 91704011407935538162643370479654133141199787581582435133179259436830137748246 238
UVM_ERROR @ 2200133202 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 2200133202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 45117088378748891006796784870930695034566645058088736417906099222420501553238 316
UVM_ERROR @ 9760461803 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 9760461803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 58134645162804372470135896640115577602127286021571106441474581877429957996581 203
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---