Simulation Results: kmac

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.34 %
  • code
  • 92.17 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.81%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 63.840s 3635.966us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.350s 35.610us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.370s 18.370us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 12.970s 1337.769us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.710s 1611.561us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.880s 75.690us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.370s 18.370us 20 20 100.00
kmac_csr_aliasing 6.710s 1611.561us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.070s 18.414us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.920s 165.959us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3030.850s 133738.804us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 997.440s 206080.432us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1822.900s 105380.847us 5 5 100.00
kmac_test_vectors_sha3_256 1147.670s 67783.220us 5 5 100.00
kmac_test_vectors_sha3_384 1265.850s 188780.016us 5 5 100.00
kmac_test_vectors_sha3_512 660.210s 147606.481us 5 5 100.00
kmac_test_vectors_shake_128 2069.520s 72198.246us 5 5 100.00
kmac_test_vectors_shake_256 1663.750s 440748.788us 5 5 100.00
kmac_test_vectors_kmac 2.940s 156.493us 5 5 100.00
kmac_test_vectors_kmac_xof 3.060s 108.192us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 393.830s 13913.404us 50 50 100.00
app 50 50 100.00
kmac_app 393.330s 19103.273us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 280.670s 154560.761us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 299.500s 14414.704us 50 50 100.00
error 50 50 100.00
kmac_error 360.620s 14546.854us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 15.470s 14325.882us 49 50 98.00
sideload_invalid 41 50 82.00
kmac_sideload_invalid 135.500s 10117.329us 41 50 82.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.510s 2363.806us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 37.950s 1970.362us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 54.480s 77913.525us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 54.620s 970.268us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 1822.090s 137735.823us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.110s 14.329us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.280s 53.827us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.840s 284.404us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.840s 284.404us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.350s 35.610us 5 5 100.00
kmac_csr_rw 1.370s 18.370us 20 20 100.00
kmac_csr_aliasing 6.710s 1611.561us 5 5 100.00
kmac_same_csr_outstanding 2.900s 437.430us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.350s 35.610us 5 5 100.00
kmac_csr_rw 1.370s 18.370us 20 20 100.00
kmac_csr_aliasing 6.710s 1611.561us 5 5 100.00
kmac_same_csr_outstanding 2.900s 437.430us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.550s 82.633us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.550s 82.633us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.550s 82.633us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.550s 82.633us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.390s 699.488us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 63.660s 4732.226us 5 5 100.00
kmac_tl_intg_err 5.010s 488.776us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.010s 488.776us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 54.620s 970.268us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 63.840s 3635.966us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 393.830s 13913.404us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.550s 82.633us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 63.660s 4732.226us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 63.660s 4732.226us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 63.660s 4732.226us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 63.840s 3635.966us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 54.620s 970.268us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 63.660s 4732.226us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 189.520s 3150.790us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 63.840s 3635.966us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 222.450s 8639.609us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 63936475781584882121039382033160305989167318985676177341110907896555123167810 92
UVM_ERROR @ 2717510268 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2717510268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9)
kmac_sideload_invalid 44359882506090428958647424120907147441986288988543673495536246051313383823838 83
UVM_FATAL @ 10187153053 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5fc0000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10187153053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 108900576015000396178056661722599707833984405186677371839241713744289547451067 387
UVM_ERROR @ 41153014758 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 41153014758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19)
kmac_sideload_invalid 68532019226003532062751153578735480428227919200503890058376748753056418811916 94
UVM_FATAL @ 10117328799 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x828ef000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
UVM_INFO @ 10117328799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 82520653161339183363489194830993136006565613838420151437230238751914058146753 76
UVM_FATAL @ 10064958524 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdfe16000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10064958524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 4897242209415931178299149645289299126028932295236183682171148852090258386403 75
UVM_FATAL @ 10008257178 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa0de5000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008257178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 81040712211534265512181291624028752110758698840102539832257211389987892289938 75
UVM_FATAL @ 10033804252 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x573c1000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10033804252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=31)
kmac_sideload_invalid 111972970286115700549342499347637064681543757584821530100779080153487065632902 108
UVM_FATAL @ 10645478308 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x753b9000, Comparison=CompareOpEq, exp_data=0x1, call_count=31)
UVM_INFO @ 10645478308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 95352596091217334045706450308545170284729118115812457546994563459908420244782 78
UVM_FATAL @ 10086495901 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4070b000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10086495901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21)
kmac_sideload_invalid 112963076022247930937136931688303521948887766501995710630868841949483376508956 97
UVM_FATAL @ 11269711099 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x65ba4000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 11269711099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 23931610939895370702915133421119756334358686069377707718995283158425312422251 90
UVM_ERROR @ 2922255767 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 2922255767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 65046433743334716893928642821664064233570459858014792636265951499119829678292 90
UVM_FATAL @ 10793861443 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4b658000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10793861443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---