Simulation Results: otbn

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 97.19 %
  • assert
  • 89.83 %
  • func
  • 100.00 %
  • block
  • 99.61 %
  • line
  • 99.70 %
  • branch
  • 95.50 %
  • toggle
  • 93.54 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.13%
V2S
94.92%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 287.012us 1 1 100.00
single_binary 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 4.000s 22.300us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 6.000s 25.100us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 7.000s 63.074us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 5.000s 21.583us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 38.073us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 6.000s 25.100us 20 20 100.00
otbn_csr_aliasing 5.000s 21.583us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 43.000s 2441.805us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 21.000s 5289.930us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 9 10 90.00
otbn_reset 52.000s 229.644us 9 10 90.00
multi_error 1 1 100.00
otbn_multi_err 53.000s 342.516us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 112.000s 246.176us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 114.000s 391.693us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 14.000s 219.936us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 16.645us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 20.000s 67.851us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 5.000s 25.045us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 5.000s 20.215us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 8.000s 117.732us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 8.000s 117.732us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 4.000s 22.300us 5 5 100.00
otbn_csr_rw 6.000s 25.100us 20 20 100.00
otbn_csr_aliasing 5.000s 21.583us 5 5 100.00
otbn_same_csr_outstanding 5.000s 19.528us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 4.000s 22.300us 5 5 100.00
otbn_csr_rw 6.000s 25.100us 20 20 100.00
otbn_csr_aliasing 5.000s 21.583us 5 5 100.00
otbn_same_csr_outstanding 5.000s 19.528us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 14.000s 31.053us 10 10 100.00
otbn_dmem_err 18.000s 92.809us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 11.000s 89.510us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 63.138us 5 5 100.00
otbn_mac_bignum_acc_err 102.000s 432.360us 5 5 100.00
otbn_urnd_err 7.000s 19.991us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.015us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 45.529us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 9.000s 44.308us 9 10 90.00
tl_intg_err 21 25 84.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
otbn_tl_intg_err 32.000s 230.959us 20 20 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 63.000s 315.056us 18 20 90.00
prim_fsm_check 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
prim_count_check 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 287.012us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 18.000s 92.809us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 14.000s 31.053us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 32.000s 230.959us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 14.000s 219.936us 59 60 98.33
sec_cm_controller_fsm_local_esc 36 40 90.00
otbn_imem_err 14.000s 31.053us 10 10 100.00
otbn_dmem_err 18.000s 92.809us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 16.645us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.015us 5 5 100.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_controller_fsm_sparse 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 14.000s 31.053us 10 10 100.00
otbn_dmem_err 18.000s 92.809us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 16.645us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.015us 5 5 100.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_scramble_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 14.000s 219.936us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 14.000s 31.053us 10 10 100.00
otbn_dmem_err 18.000s 92.809us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 16.645us 5 5 100.00
otbn_illegal_mem_acc 7.000s 25.015us 5 5 100.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 11.000s 38.212us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 20.000s 77.049us 5 5 100.00
sec_cm_rnd_bus_consistency 4 5 80.00
otbn_rnd_sec_cm 95.000s 366.576us 4 5 80.00
sec_cm_rnd_rng_digest 4 5 80.00
otbn_rnd_sec_cm 95.000s 366.576us 4 5 80.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 10.000s 21.144us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_stack_wr_ptr_ctr_redun 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 11.000s 58.975us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_loop_stack_ctr_redun 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 8.000s 107.732us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 8.000s 107.732us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 5 7 71.43
otbn_sec_wipe_err 23.000s 58.714us 5 7 71.43
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 112.000s 246.176us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 8.000s 33.439us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 253.000s 926.726us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
otbn_sec_cm 130.000s 2366.768us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 447.000s 9035.880us 2 10 20.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_rnd_sec_cm 83227847678738148247064747380534616699699589181292048489101834695562372860921 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 83227847678738148247064747380534616699699589181292048489101834695562372860921 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1692945401 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_rnd_sec_cm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_rnd_sec_cm.1692945401 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_rnd_sec_cm.1692945401 -covoverwrite' seed=83227847678738148247064747380534616699699589181292048489101834695562372860921 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_rnd_sec_cm_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 83227847678738148247064747380534616699699589181292048489101834695562372860921 --size 2000 --count 1 /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest
2025/12/28 13:10:17 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 84428571654168478521736017472026901313696256265891531202155287788638395007883 101
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 44081052 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 44081052 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 44081052 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 44081052 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 44081052 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 60232215111086510201703948116582392189255462790340888034162968031582174644485 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 300527220 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 300527220 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 300527220 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 300527220 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 300527220 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 75891968225778252883193601742845927113474712550859403195857341722505978401082 95
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 32600499 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 32600499 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 32600499 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 32600499 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 32600499 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 80485683909121870877693156431904459911603472122024006783860379594507339091035 84
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 4070276 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 4070276 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 4070276 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 4070276 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 4070276 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 105408350685908290730755484027631363040862816305219845798557288460584936882582 208
UVM_ERROR @ 329623427 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 329623427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 8469042046192883849833313081019898315436071059741172638105883314525597893577 196
UVM_ERROR @ 533898507 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 533898507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 102518853020464178098789210674524186342567692406504328656097369673094634084349 171
UVM_ERROR @ 488279831 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 488279831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 115453320757411827874831004439661255565638116024146233096810159819488552010944 473
UVM_ERROR @ 891250771 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 891250771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 76034246105409441856310172125133064607487931207031319288229137055769441869182 272
UVM_ERROR @ 4814613216 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4814613216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 50510482186203578599839720470107716426918148745787072859874256654673895343664 111
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 58714042 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 58714042 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 58714042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 36239880217220322739587545918443825402957484098384263828632157806113996130238 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15708675 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 15708675 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 15708675 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 15708675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 90544201759181424986590054863591809386757455441433119657431248547549579773005 116
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39844895 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 39844895 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 39844895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 51923659584292794416681052960155892644368297036263855172274357951194917748724 287
UVM_FATAL @ 385886040 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 385886040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 50795566004838410741283081474493279872344089072910967751421652042759019860346 445
UVM_FATAL @ 2405184675 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2405184675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_multi 105190947173082900312375122913115703210502789682819021426568669831938855771834 165
UVM_FATAL @ 108510756 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 108510756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 52556736166982519939156719811940765753056580158840045627197371648353807545869 380
UVM_FATAL @ 1207288231 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1207288231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 14272049675862202132199736614746577524734463482224287625091039182738849379838 93
UVM_FATAL @ 115199251 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 115199251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
otbn_reset 55810409342194832843750330922347341814504323068237461059516374898992634269563 138
UVM_FATAL @ 229643808 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
UVM_INFO @ 229643808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 60639579257958817113353928314702038980587905054287095905036762062870069528514 112
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 7130812 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 7130812 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7130812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_escalate 78180418884786483447002363656825670255864190906154481208788576097651744881321 109
UVM_ERROR @ 4872206 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 4872206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 22916921224474339849633633168545430510166701783845003621147725810154863540357 93
UVM_FATAL @ 77363941 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 77363941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---