Simulation Results: rom_ctrl

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.68 %
  • code
  • 98.74 %
  • assert
  • 95.49 %
  • func
  • 98.81 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.39 %
  • toggle
  • 99.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
74.84%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.170s 181.489us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.580s 184.284us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.880s 542.326us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.780s 2002.149us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.670s 170.756us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.350s 713.722us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.880s 542.326us 20 20 100.00
rom_ctrl_csr_aliasing 5.670s 170.756us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.830s 348.277us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.760s 537.183us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 4.740s 136.142us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 25.280s 2068.528us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.930s 1436.511us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.470s 2081.662us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.660s 244.292us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.660s 244.292us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.580s 184.284us 5 5 100.00
rom_ctrl_csr_rw 6.880s 542.326us 20 20 100.00
rom_ctrl_csr_aliasing 5.670s 170.756us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.610s 292.496us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.580s 184.284us 5 5 100.00
rom_ctrl_csr_rw 6.880s 542.326us 20 20 100.00
rom_ctrl_csr_aliasing 5.670s 170.756us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.610s 292.496us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.480s 4779.397us 20 20 100.00
tl_intg_err 20 25 80.00
rom_ctrl_tl_intg_err 65.990s 631.167us 20 20 100.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
prim_fsm_check 0 5 0.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
prim_count_check 0 5 0.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
sec_cm_checker_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_checker_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_checker_fsm_local_esc 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_compare_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_compare_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_compare_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.170s 181.489us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.170s 181.489us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.170s 181.489us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 65.990s 631.167us 20 20 100.00
sec_cm_bus_local_esc 17 22 77.27
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
rom_ctrl_kmac_err_chk 9.930s 1436.511us 2 2 100.00
sec_cm_mux_mubi 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_mux_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_ctrl_redun 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 148.960s 2743.741us 15 20 75.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.480s 4779.397us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 250.940s 1243.419us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 323.610s 9169.069us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 59246414666989083609486614571817662851598725210462552319446107848136484035829 303
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 44581414ps failed at 44581414ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 44581414ps failed at 44581414ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 7366164832355076937143798215620715868327193160321153739308081732427211830299 238
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 53736901ps failed at 53736901ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 53736901ps failed at 53736901ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 4721275189440787615943951117332420545841867537372974627524034561703478724595 108
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 4806877ps failed at 4806877ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 4806877ps failed at 4806877ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 98149693735282153598312865516343407410895729870616910678670932540816062472002 127
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 5832811ps failed at 5832811ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 5832811ps failed at 5832811ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 57938256123867453089477518642817226139393793338118022786924458918911711314138 220
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 7294422ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 7294422ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 7294422ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 16443934728698082677689136815661205414825620288873244322066145203779043094411 101
UVM_ERROR @ 1725041100 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1725041100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 35597374744933142904949727228316507187935552211199870704680589753477916060208 83
UVM_ERROR @ 4810231533 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 4810231533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 2877164661671551213638016168437719439767165922810780715368234269561881625414 101
UVM_ERROR @ 4158380503 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 4158380503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 24886058459469876283069888028822366166154087079638441771517516677083246360977 89
UVM_ERROR @ 976555750 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 976555750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 72191346877447073653256328602200668406646255965438443945227940851605947421361 75
UVM_ERROR @ 1061474663 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1061474663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---