rom_ctrl Simulation Results

Simulation Results: rom_ctrl

28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.68 %

code
98.74 %

assert
95.49 %

func
98.81 %

line
99.46 %

branch
99.27 %

cond
95.39 %

toggle
99.59 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		90.57%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	12.660s	1107.703us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	12.540s	295.249us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	13.990s	2040.254us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	11.550s	293.675us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	9.600s	1070.259us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	11.180s	293.312us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	13.990s	2040.254us	20	20	100.00
	rom_ctrl_csr_aliasing	9.600s	1070.259us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	10.560s	546.451us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	11.320s	288.922us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	10.650s	234.840us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	51.460s	4205.854us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	18.510s	552.210us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	16.310s	14227.621us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	16.270s	298.076us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	16.270s	298.076us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	12.540s	295.249us	5	5	100.00
	rom_ctrl_csr_rw	13.990s	2040.254us	20	20	100.00
	rom_ctrl_csr_aliasing	9.600s	1070.259us	5	5	100.00
	rom_ctrl_same_csr_outstanding	14.480s	219.206us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	12.540s	295.249us	5	5	100.00
	rom_ctrl_csr_rw	13.990s	2040.254us	20	20	100.00
	rom_ctrl_csr_aliasing	9.600s	1070.259us	5	5	100.00
	rom_ctrl_same_csr_outstanding	14.480s	219.206us	20	20	100.00

V2S

288/318 passed

90.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	58.620s	1714.097us	20	20	100.00
tl_intg_err				20	25	80.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00
	rom_ctrl_tl_intg_err	160.540s	386.944us	20	20	100.00
prim_fsm_check				0	5	0.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00
prim_count_check				0	5	0.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_compare_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00
sec_cm_fsm_sparse				0	5	0.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	12.660s	1107.703us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	12.660s	1107.703us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	12.660s	1107.703us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	160.540s	386.944us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
	rom_ctrl_kmac_err_chk	18.510s	552.210us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	230.340s	18370.798us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	58.620s	1714.097us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	rom_ctrl_sec_cm	271.870s	8688.716us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	418.860s	12335.431us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	90981676733168304064106871995692660991227225682713118820002124878668477109587	304	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 50015524ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 50015524ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120)) Starting assertion attempts at time 50015524ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	31223436104465397329973281407569009861144661814071529364682187040870290211606	289	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 117106968ps failed at 117106968ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 117173635ps failed at 117173635ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	114587407445443090219144513531568597951009594432935048481623632007955206194229	188	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 28064490ps failed at 28064490ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 32371547ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 32371547ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	13558954405335668276182747802061098635252603114715206904039315553965128325170	238	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 51583154ps failed at 51583154ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 51583154ps failed at 51583154ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	37755804417750664232211504942313529870919951091376359950997146815079643013496	230	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 17507031ps failed at 17507031ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17507031ps failed at 17507031ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'