Simulation Results: rstmgr

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.590s 258.616us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 0.870s 152.288us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 6.400s 2311.887us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.800s 369.582us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.540s 200.870us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00
rstmgr_csr_aliasing 1.800s 369.582us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.210s 169.822us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.200s 451.249us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.450s 130.241us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.640s 1828.508us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.640s 1828.508us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.640s 1828.508us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.640s 1828.508us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 38.110s 14880.950us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.100s 108.402us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.930s 614.571us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.930s 614.571us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 0.870s 152.288us 5 5 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00
rstmgr_csr_aliasing 1.800s 369.582us 5 5 100.00
rstmgr_same_csr_outstanding 1.430s 223.370us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 0.870s 152.288us 5 5 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00
rstmgr_csr_aliasing 1.800s 369.582us 5 5 100.00
rstmgr_same_csr_outstanding 1.430s 223.370us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 25.560s 16894.421us 5 5 100.00
rstmgr_tl_intg_err 2.930s 1153.462us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 25.560s 16894.421us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 25.560s 16894.421us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 2.930s 1153.462us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.360s 184.662us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.890s 2455.135us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.390s 301.042us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 25.560s 16894.421us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.850s 86.610us 20 20 100.00

Error Messages

   Test seed line log context