rstmgr_cnsty_chk Simulation Results

Simulation Results: rstmgr_cnsty_chk

28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.52 %

code
95.05 %

assert
100.00 %

line
98.41 %

branch
98.31 %

cond
86.21 %

toggle
100.00 %

FSM
92.31 %

Validation stages

unmapped

80.00%

unmapped

8/10 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				8	10	80.00
	rstmgr_cnsty_chk_test	2.650s	11070.276us	8	10	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == *))
	rstmgr_cnsty_chk_test	94612636770986748951164563156918280880377960831175643374981960073404119796969	172	UVM_ERROR @ 1750616248 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1768216248 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1785816248 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 1803416248 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 1821016248 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
	rstmgr_cnsty_chk_test	83526854195217686715821899131078076406759277781574191515453029596447164338857	172	UVM_ERROR @ 1956931851 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) \|\| (delta_cycles > -1) \|\| (error_count == 0)) UVM_INFO @ 1976611851 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16 UVM_INFO @ 1996291851 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16 UVM_INFO @ 2015971851 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16 UVM_INFO @ 2035651851 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16