Simulation Results: spi_device

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 94.28 %
  • assert
  • 94.41 %
  • func
  • 99.26 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.66 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.91%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 624.100s 82201.272us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.150s 151.404us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.300s 324.193us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 25.330s 1808.516us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 15.830s 927.438us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.060s 124.438us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.300s 324.193us 20 20 100.00
spi_device_csr_aliasing 15.830s 927.438us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.840s 85.438us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 1.710s 219.758us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.200s 22.936us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.450s 58.822us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.130s 26.956us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.010s 247.306us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.010s 247.306us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 18.900s 7130.542us 50 50 100.00
spi_device_tpm_sts_read 1.370s 79.301us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 44.550s 45495.688us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 33.400s 31285.935us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 26.660s 36341.548us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 26.660s 36341.548us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 28.960s 41462.094us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 28.960s 41462.094us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 28.960s 41462.094us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 28.960s 41462.094us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 28.960s 41462.094us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 34.420s 34551.589us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 108.160s 57567.559us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 108.160s 57567.559us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 108.160s 57567.559us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 34.510s 3528.774us 50 50 100.00
spi_device_read_buffer_direct 16.060s 1932.501us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 108.160s 57567.559us 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 208.870s 32416.053us 50 50 100.00
4b_3b_feature 49 50 98.00
spi_device_cfg_cmd 21.300s 1893.590us 49 50 98.00
write_enable_disable 49 50 98.00
spi_device_cfg_cmd 21.300s 1893.590us 49 50 98.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 624.100s 82201.272us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 301.690s 164652.717us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 1105.580s 142030.265us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.140s 95.785us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 0.940s 77.398us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.550s 465.002us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.550s 465.002us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.150s 151.404us 5 5 100.00
spi_device_csr_rw 2.300s 324.193us 20 20 100.00
spi_device_csr_aliasing 15.830s 927.438us 5 5 100.00
spi_device_same_csr_outstanding 3.470s 973.130us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.150s 151.404us 5 5 100.00
spi_device_csr_rw 2.300s 324.193us 20 20 100.00
spi_device_csr_aliasing 15.830s 927.438us 5 5 100.00
spi_device_same_csr_outstanding 3.470s 973.130us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 17.480s 1094.440us 20 20 100.00
spi_device_sec_cm 1.940s 694.593us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 17.480s 1094.440us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 400.840s 295460.339us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}}
spi_device_cfg_cmd 105390678945960211793312816891875004263689019515528662852140773226053185725088 78
UVM_ERROR @ 5756622391 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc21d6a) != exp '{'{other_status:'h116679, wel:'h1, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h7eaa7, wel:'h0, busy:'h0}}
UVM_ERROR @ 5760844609 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc21d6a) != exp '{'{other_status:'h116679, wel:'h1, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h7eaa7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 5762177941 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc21d6a) != exp '{'{other_status:'h116679, wel:'h1, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h7eaa7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 5764511272 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e0a9e) != exp '{'{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}, '{other_status:'h7eaa7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 5765289049 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6e0a9e) != exp '{'{other_status:'h30875a, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}, '{other_status:'h7eaa7, wel:'h0, busy:'h0}, '{other_status:'h1b82a7, wel:'h0, busy:'h0}}