Simulation Results: sram_ctrl

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.23%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 100.000s 5498.561us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.860s 51.095us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 0.920s 36.824us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 1.800s 417.389us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 0.790s 36.746us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.280s 6928.141us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 0.920s 36.824us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 36.746us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 457.120s 359310.958us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 176.650s 17432.292us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1394.440s 25579.065us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 381.920s 20708.366us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2441.260s 351661.394us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1638.470s 17602.609us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 117.420s 19288.988us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1321.250s 32426.370us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 85.920s 2087.673us 50 50 100.00
sram_ctrl_partial_access_b2b 663.680s 370847.759us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 92.980s 4246.433us 50 50 100.00
sram_ctrl_throughput_w_partial_write 111.370s 1667.590us 50 50 100.00
sram_ctrl_throughput_w_readback 103.530s 1807.073us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1344.220s 17497.828us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.840s 5604.224us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 8886.120s 742160.499us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.080s 23.405us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 3.550s 577.532us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 3.550s 577.532us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.860s 51.095us 5 5 100.00
sram_ctrl_csr_rw 0.920s 36.824us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 36.746us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.070s 85.678us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.860s 51.095us 5 5 100.00
sram_ctrl_csr_rw 0.920s 36.824us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 36.746us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.070s 85.678us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 48.890s 47049.737us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 2.790s 1972.728us 20 20 100.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 2.790s 1972.728us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1344.220s 17497.828us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1344.220s 17497.828us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 0.920s 36.824us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1321.250s 32426.370us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1321.250s 32426.370us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1321.250s 32426.370us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 117.420s 19288.988us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 47 50 94.00
sram_ctrl_mubi_enc_err 9.470s 2353.454us 47 50 94.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 48.890s 47049.737us 20 20 100.00
sec_cm_mem_readback 38 50 76.00
sram_ctrl_readback_err 9.120s 2769.835us 38 50 76.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 100.000s 5498.561us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 100.000s 5498.561us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1321.250s 32426.370us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 117.420s 19288.988us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 100.000s 5498.561us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.180s 6.247us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 146.650s 2751.965us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 57146692239818879935858537944156416461618493081979450505286932633071101850292 99
UVM_ERROR @ 8774025 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 8774025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 101296415216110544822242754661203921213636666695184708584657904956410331023815 97
UVM_ERROR @ 7271676 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 7271676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 90556741185237844516020917486300498003861520945310407909315591894820058757457 95
UVM_ERROR @ 876929346 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x34)
UVM_INFO @ 876929346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 45940366185123995951351840574279123681051709256034547623489839031387301813405 95
UVM_ERROR @ 6576264276 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4) != exp (0x6a)
UVM_INFO @ 6576264276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 114386809983773265212270483042799958649193302086858091700413125551419722605691 95
UVM_ERROR @ 674145064 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x68) != exp (0xc)
UVM_INFO @ 674145064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 46640934039957796159751754724748756441502454180251357452352723667235457975687 95
UVM_ERROR @ 4106657190 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x8)
UVM_INFO @ 4106657190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 60673958878672119814202779054346428110246538861921622255338648906252191389750 95
UVM_ERROR @ 664908773 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x0) != exp (0x14)
UVM_INFO @ 664908773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 101200647114170961265903270113932081760380803958860425551283808587393630924586 95
UVM_ERROR @ 3648695041 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3b) != exp (0xf)
UVM_INFO @ 3648695041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 8200668514762650979266583872523579088907057946425628826462345553488029401571 95
UVM_ERROR @ 666430688 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x3f)
UVM_INFO @ 666430688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 99953313612129100285290377955964930828141943187754640831842494597444694762976 95
UVM_ERROR @ 2638799368 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x23) != exp (0x7f)
UVM_INFO @ 2638799368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 64825230788690760206988578202123763679624135027499982106233360512946490891246 95
UVM_ERROR @ 684310222 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x62) != exp (0x32)
UVM_INFO @ 684310222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 98412374640568332108418145151444829301734062317821750722073502581075993392810 95
UVM_ERROR @ 3870120327 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x25)
UVM_INFO @ 3870120327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 66756617683996554764149918099769206413339519825551581487291591282210390663162 95
UVM_ERROR @ 3283073210 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x60) != exp (0x66)
UVM_INFO @ 3283073210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44085008247526752168301518117094128728459880750315907715296818224885702275455 95
UVM_ERROR @ 2529160326 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x33)
UVM_INFO @ 2529160326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 92622575371357742871512168145212337655245885266280751344363924885233373839677 99
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 6246680 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 6246680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 49351340453077811294435318447891596868638144204059363751988137062834857037138 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3500589 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3500589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 70210391916413405655573402960348886777338847254858177319001423270521048081692 101
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 13813484 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 13813484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 60064148832653706732034007511642939812569303809349677797979923704549457534104 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2651128149 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2651128149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 66324650263556466835216119396997224717743922590026816036647380395444745810238 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 795113922 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 795113922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 88579202704743065814841083706106006394565392723200796476140353614889265444036 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2634943812 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2634943812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---