Simulation Results: sram_ctrl

 
28/12/2025 00:10:32 sha: 3043786 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.75 %
  • code
  • 96.12 %
  • assert
  • 95.79 %
  • func
  • 98.33 %
  • line
  • 99.07 %
  • branch
  • 97.98 %
  • cond
  • 92.90 %
  • toggle
  • 90.66 %
  • FSM
  • 100.00 %
Validation stages
V1
99.57%
V2
99.89%
V2S
93.59%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 87.730s 2511.173us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 0.810s 14.736us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 0.890s 31.710us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.020s 42.719us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 0.960s 137.321us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.900s 91.608us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 0.890s 31.710us 20 20 100.00
sram_ctrl_csr_aliasing 0.960s 137.321us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 12.540s 694.154us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 8.080s 192.989us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1175.110s 139221.560us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 388.250s 4088.101us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 82.160s 18277.058us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1093.950s 77594.226us 50 50 100.00
lc_escalation 49 50 98.00
sram_ctrl_lc_escalation 10.930s 3506.502us 49 50 98.00
executable 50 50 100.00
sram_ctrl_executable 1500.030s 78572.682us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 99.040s 3105.089us 50 50 100.00
sram_ctrl_partial_access_b2b 517.550s 88598.836us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 96.660s 920.840us 50 50 100.00
sram_ctrl_throughput_w_partial_write 95.520s 1789.613us 50 50 100.00
sram_ctrl_throughput_w_readback 94.070s 3812.304us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1353.580s 44455.252us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 1.180s 27.217us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 3663.000s 265955.818us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.080s 16.256us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 3.480s 140.654us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 3.480s 140.654us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.810s 14.736us 5 5 100.00
sram_ctrl_csr_rw 0.890s 31.710us 20 20 100.00
sram_ctrl_csr_aliasing 0.960s 137.321us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.030s 25.951us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 0.810s 14.736us 5 5 100.00
sram_ctrl_csr_rw 0.890s 31.710us 20 20 100.00
sram_ctrl_csr_aliasing 0.960s 137.321us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.030s 25.951us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.160s 541.318us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_tl_intg_err 2.130s 382.267us 20 20 100.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 2.130s 382.267us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1353.580s 44455.252us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1353.580s 44455.252us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 0.890s 31.710us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1500.030s 78572.682us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1500.030s 78572.682us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1500.030s 78572.682us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
sram_ctrl_lc_escalation 10.930s 3506.502us 49 50 98.00
sec_cm_prim_ram_ctrl_mubi 45 50 90.00
sram_ctrl_mubi_enc_err 1.590s 100.129us 45 50 90.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.160s 541.318us 20 20 100.00
sec_cm_mem_readback 37 50 74.00
sram_ctrl_readback_err 1.590s 45.325us 37 50 74.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 87.730s 2511.173us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 87.730s 2511.173us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1500.030s 78572.682us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
sec_cm_key_global_esc 49 50 98.00
sram_ctrl_lc_escalation 10.930s 3506.502us 49 50 98.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 87.730s 2511.173us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.760us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 676.210s 2206.008us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
sram_ctrl_csr_mem_rw_with_rand_reset 41945647378179391078553403106884632397523296818412785038492291946122695511115 95
UVM_ERROR @ 92134141 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 92134141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 20988023945787749464844243877815398042486802331223516705849704222200796789222 96
UVM_ERROR @ 6865055 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6865055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 16749516281377547185183914283106477540182716374459445720972861364761426968962 97
UVM_ERROR @ 21642951 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 21642951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 100837454521385718801560828486445482435581660342601938141062595808842042601599 96
UVM_ERROR @ 9435057 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 9435057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 106850596246465281049529127150151584936928581695043554880887113226116267922381 97
UVM_ERROR @ 1760302 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1760302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 2287004290520623666356139071332184747992416067028543863681338593212406898963 95
UVM_ERROR @ 94148446 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x42)
UVM_INFO @ 94148446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 47703947209371183271915132573051638237301714857435174457152511279610341864736 95
UVM_ERROR @ 22064305 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x7b)
UVM_INFO @ 22064305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 100741335299210635289308299836144548381297713261999258546620235316785506311359 95
UVM_ERROR @ 103817292 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x70) != exp (0x26)
UVM_INFO @ 103817292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 104866213483593919686538430649100906299362444044585986332609133455987953087255 95
UVM_ERROR @ 214039588 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1e) != exp (0x55)
UVM_INFO @ 214039588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 87434495780653500905102290425132279410544877392311013119100217924971428229135 95
UVM_ERROR @ 119577524 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1f) != exp (0x73)
UVM_INFO @ 119577524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 62790302649522196771624374425795125042560851409736534590953637148595992600465 95
UVM_ERROR @ 49363620 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x28) != exp (0x3)
UVM_INFO @ 49363620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 5728599800972767516315521969412991412343371510363818707617764381245275969384 95
UVM_ERROR @ 44930732 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5) != exp (0x3f)
UVM_INFO @ 44930732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 79838777334801000572181481010766217411359355392545777308301555173402686716952 95
UVM_ERROR @ 24868426 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x27) != exp (0x16)
UVM_INFO @ 24868426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 74234631311835458138933108499640022673984057079413725036278514577989009226581 95
UVM_ERROR @ 25174934 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x8) != exp (0x4f)
UVM_INFO @ 25174934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 78031085105036414891838213559599608944567797685586821779152863001353145627369 95
UVM_ERROR @ 24611656 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4e) != exp (0x68)
UVM_INFO @ 24611656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 41149044238417561418851357855763339218100148522202101723512776585254078192351 95
UVM_ERROR @ 97831269 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6e) != exp (0x4)
UVM_INFO @ 97831269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 76888181137540259548078415266406971524072742420930446050671435380658397158401 95
UVM_ERROR @ 160389134 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x41) != exp (0x14)
UVM_INFO @ 160389134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 69030531067648700388100511334204748254099422274606125073481848073241108139968 95
UVM_ERROR @ 94818414 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x71) != exp (0x4b)
UVM_INFO @ 94818414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 48771226367075470936250705319502728445583142787513124763351563971623240341484 98
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 3986637ps failed at 3986637ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 4751637 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4751637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch
sram_ctrl_lc_escalation 58560414770687916668847450331344840015792128848436479027634378862017586770199 93
UVM_ERROR @ 3219725345 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x46 [1000110] vs 0xf7 [11110111]) addr 0xde726d7c read out mismatch
UVM_INFO @ 3219725345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 14055702134130316580846236417427306209635274663401184841153762529824199618817 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 94364643 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 94364643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 38647499611750431550568993705125300656583113939469352396937462387796124651133 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 380175041 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 380175041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 73146741547783516088338147894444738245609624109089266846577518358288451881920 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 34861918 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 34861918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 59887033360306165794898813024517535143028642354870773782758509272560651181581 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 36639013 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 36639013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3052) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_mubi_enc_err 94370706927701123719748767562763001067970063512469735413551977483537732180499 100
UVM_ERROR @ 110258469 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3052) { a_addr: 'ha0c57514 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'haf a_opcode: 'h4 a_user: 'h275aa d_param: 'h0 d_source: 'haf d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 110258469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---