Simulation Results: adc_ctrl

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.62 %
  • code
  • 98.74 %
  • assert
  • 95.95 %
  • func
  • 92.18 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 96.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.50%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 20.630s 5899.842us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 3.560s 1263.705us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.550s 473.443us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 151.620s 52735.730us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 3.280s 958.640us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.130s 532.819us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.550s 473.443us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 958.640us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1407.200s 486605.095us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1074.690s 498560.287us 50 50 100.00
filters_interrupt 50 50 100.00
adc_ctrl_filters_interrupt 1235.060s 502174.702us 50 50 100.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1225.310s 489771.839us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1275.740s 619450.695us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1391.160s 594932.714us 50 50 100.00
filters_both 50 50 100.00
adc_ctrl_filters_both 1292.540s 516932.054us 50 50 100.00
clock_gating 31 50 62.00
adc_ctrl_clock_gating 1246.180s 517786.137us 31 50 62.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 17.110s 5333.790us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 145.370s 44646.771us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 420.570s 129398.692us 50 50 100.00
stress_all 48 50 96.00
adc_ctrl_stress_all 1720.460s 10000000.000us 48 50 96.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.500s 519.308us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 2.490s 506.795us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.050s 696.435us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.050s 696.435us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.560s 1263.705us 5 5 100.00
adc_ctrl_csr_rw 2.550s 473.443us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 958.640us 5 5 100.00
adc_ctrl_same_csr_outstanding 14.690s 4827.115us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.560s 1263.705us 5 5 100.00
adc_ctrl_csr_rw 2.550s 473.443us 20 20 100.00
adc_ctrl_csr_aliasing 3.280s 958.640us 5 5 100.00
adc_ctrl_same_csr_outstanding 14.690s 4827.115us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_sec_cm 15.680s 7531.771us 5 5 100.00
adc_ctrl_tl_intg_err 29.830s 8825.076us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 29.830s 8825.076us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
adc_ctrl_stress_all_with_rand_reset 2037.100s 10000000.000us 41 50 82.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_clock_gating 15708168946909483521797553007434273530021704676872003956988808423327647609582 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 47133121122450365302610506578614133668803437917524125693794325214534542167523 331
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 19062191354606532602605538643683818397934190726087962597891828620217362994079 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 76324590563027294437171629200762882164300134009808596986188741151462414991940 376
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 46497322741857978540735133253412033209627077121378463236654732681115470899904 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 2378388082281975174340235874211594829762137608681719924413982470325219575390 353
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 14971330000399147751797249884154534698889388588799429167788692849510606003195 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 48251272592196023367775621992557096305816506837034988104146638744327094747827 379
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 51076346133471710155968939351270123265798079568150439925776004036413063762839 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 114898880974928005296869144948824155021530374077841718871834508485502011112331 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 93792850283938873057816174246740634486952688522949365395066863117139933469924 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 94313039466078071902167010157993600008700921887367625561227677295526356387891 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 54612205340169165764872175865454525883707352446773496794964308112018052978977 376
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 112091436623429677875903280432302095213104478781667703358686931481198582205484 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 9112656334830427059853362422834424375078624062525140620119825215662809553178 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 24212667238722921466327968473905573814974817912065056118404783459515064772122 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 25709198573922230111410053260497533461645183640297602101053498016570089705684 355
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 50941079086668977854684810960833126566618483505516559914584424244599842838962 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 72707388749374657254571849894947973973015254181606806730803973004186320852567 335
UVM_ERROR @ 187170578765 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 187170578765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 15891164306604811314926428237104866621120059839672604162067571794961426749108 328
UVM_ERROR @ 4604742845 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4604742845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 92677588896882877753733174845078229200861870848545254000425212052820141831090 318
UVM_ERROR @ 1390215455 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 1390215455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 16975237080115012769384892435145040119470034183635633933480264253320748321526 318
UVM_ERROR @ 2741066792 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2741066792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 87202224052850503302298228079272306415866418928344516631378963063041840020676 402
UVM_ERROR @ 41201862019 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 41201862019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 19163094079999010743500415656150624792178278306707774528932764828789945475590 318
UVM_ERROR @ 907785025 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 907785025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 105830882847762923611254577495149922948049631745855316539948216041658274264748 335
UVM_ERROR @ 166055123026 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 166055123026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 38212074664798791092507200335465464119233837387394546860160719665319982631659 321
UVM_ERROR @ 9197121970 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 9197121970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 110354630992590410648373989968127160181767922548159989689289493976174917949720 377
UVM_ERROR @ 39339353441 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 39339353441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(np_sample_cnt_q == '0)'
adc_ctrl_stress_all_with_rand_reset 88285921101807528129540310809102472329255653796178526560986205481280483258583 395
Offending '(np_sample_cnt_q == '0)'
UVM_ERROR @ 3517823781 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 3517823781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_clock_gating 10529341100897640815896506887897980754788499226491501593598901789725948841607 318
UVM_ERROR @ 93239279255 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 93239279255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 39170198443002586752682250379896453834389283888444218927003471580732463641681 318
UVM_ERROR @ 81974610839 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 81974610839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---