Simulation Results: chip

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.22 %
  • code
  • 86.47 %
  • assert
  • 96.93 %
  • func
  • 99.26 %
  • line
  • 94.69 %
  • branch
  • 94.87 %
  • cond
  • 93.85 %
  • toggle
  • 91.80 %
  • FSM
  • 57.14 %
Validation stages
V1
94.92%
V2
92.10%
V2S
100.00%
V3
84.24%
unmapped
77.27%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 172.550s 2309.044us 3 3 100.00
chip_sw_example_rom 113.710s 1996.212us 3 3 100.00
chip_sw_example_manufacturer 173.080s 3063.581us 3 3 100.00
chip_sw_example_concurrency 153.060s 2821.277us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 326.470s 7338.359us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 559.930s 5545.864us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 760.070s 7629.427us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 4860.850s 28445.329us 5 5 100.00
csr_mem_rw_with_rand_reset 7 20 35.00
chip_csr_mem_rw_with_rand_reset 759.840s 9366.646us 7 20 35.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 4860.850s 28445.329us 5 5 100.00
chip_csr_rw 559.930s 5545.864us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 11.030s 235.062us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 412.050s 3875.956us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 412.050s 3875.956us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 412.050s 3875.956us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 455.720s 4644.859us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 455.720s 4644.859us 5 5 100.00
chip_sw_uart_tx_rx_idx1 525.240s 4557.836us 5 5 100.00
chip_sw_uart_tx_rx_idx2 513.030s 4728.926us 5 5 100.00
chip_sw_uart_tx_rx_idx3 494.080s 4702.283us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2128.850s 12969.827us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1283.970s 8117.311us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1515.180s 13417.339us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 201.480s 5468.492us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 201.480s 5468.492us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 1 3 33.33
chip_sw_sleep_pin_mio_dio_val 266.250s 3363.070us 1 3 33.33
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 263.000s 3462.623us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 247.980s 4054.289us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1133.370s 14922.301us 5 5 100.00
chip_tap_straps_testunlock0 506.380s 6965.352us 5 5 100.00
chip_tap_straps_rma 473.870s 6066.000us 5 5 100.00
chip_tap_straps_prod 972.970s 13538.470us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 199.120s 2929.131us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 1042.890s 8333.791us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 617.340s 6170.122us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 617.340s 6170.122us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 860.570s 8267.701us 3 3 100.00
chip_sw_ast_clk_rst_inputs 1 3 33.33
chip_sw_ast_clk_rst_inputs 2885.230s 22795.853us 1 3 33.33
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 502.220s 4570.685us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 792.830s 5538.672us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4318.810s 19168.810us 3 3 100.00
chip_sw_aes_enc_jitter_en 187.590s 3399.598us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 878.020s 5972.980us 3 3 100.00
chip_sw_hmac_enc_jitter_en 178.560s 2863.873us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1407.460s 10233.231us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.730s 2929.972us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 458.800s 5076.650us 3 3 100.00
chip_sw_clkmgr_jitter 209.830s 2633.333us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 216.860s 3364.284us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 6 8 75.00
chip_sw_sensor_ctrl_alert 817.040s 9570.317us 3 5 60.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 355.850s 5577.439us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 215.750s 3122.068us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 355.850s 5577.439us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 205.380s 3429.794us 3 3 100.00
chip_sw_aes_smoketest 253.230s 3192.811us 3 3 100.00
chip_sw_aon_timer_smoketest 245.110s 2832.458us 3 3 100.00
chip_sw_clkmgr_smoketest 144.870s 2216.811us 3 3 100.00
chip_sw_csrng_smoketest 184.000s 2691.806us 3 3 100.00
chip_sw_entropy_src_smoketest 1159.180s 7087.675us 3 3 100.00
chip_sw_gpio_smoketest 287.780s 3688.998us 3 3 100.00
chip_sw_hmac_smoketest 292.850s 3082.745us 3 3 100.00
chip_sw_kmac_smoketest 284.600s 3804.110us 3 3 100.00
chip_sw_otbn_smoketest 1851.300s 10923.022us 3 3 100.00
chip_sw_pwrmgr_smoketest 307.070s 5221.691us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 362.420s 6279.437us 3 3 100.00
chip_sw_rv_plic_smoketest 137.700s 2553.502us 3 3 100.00
chip_sw_rv_timer_smoketest 233.920s 3054.442us 3 3 100.00
chip_sw_rstmgr_smoketest 166.610s 3175.397us 3 3 100.00
chip_sw_sram_ctrl_smoketest 160.240s 2629.364us 3 3 100.00
chip_sw_uart_smoketest 195.310s 2835.431us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 153.590s 2750.615us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_functest 382.080s 5293.403us 3 3 100.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 11634.550s 61648.138us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 3664.160s 16644.916us 3 3 100.00
chip_sw_rom_raw_unlock 3 3 100.00
rom_raw_unlock 212.760s 5172.474us 3 3 100.00
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 262.660s 3767.768us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 268.190s 3207.844us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 10271.800s 55111.935us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 10521.900s 58254.910us 3 3 100.00
tl_d_oob_addr_access 3 30 10.00
chip_tl_errors 361.060s 5118.778us 3 30 10.00
tl_d_illegal_access 3 30 10.00
chip_tl_errors 361.060s 5118.778us 3 30 10.00
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 4860.850s 28445.329us 5 5 100.00
chip_same_csr_outstanding 3497.610s 29203.266us 20 20 100.00
chip_csr_hw_reset 326.470s 7338.359us 5 5 100.00
chip_csr_rw 559.930s 5545.864us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 4860.850s 28445.329us 5 5 100.00
chip_same_csr_outstanding 3497.610s 29203.266us 20 20 100.00
chip_csr_hw_reset 326.470s 7338.359us 5 5 100.00
chip_csr_rw 559.930s 5545.864us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 72.750s 2479.459us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 7.570s 56.634us 100 100 100.00
xbar_smoke_large_delays 124.790s 10860.942us 100 100 100.00
xbar_smoke_slow_rsp 98.090s 6188.692us 100 100 100.00
xbar_random_zero_delays 54.470s 605.754us 100 100 100.00
xbar_random_large_delays 485.290s 63760.140us 100 100 100.00
xbar_random_slow_rsp 441.190s 32983.834us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 57.880s 1468.202us 100 100 100.00
xbar_error_and_unmapped_addr 48.340s 1432.233us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 82.640s 2594.555us 100 100 100.00
xbar_error_and_unmapped_addr 48.340s 1432.233us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 109.310s 2333.228us 100 100 100.00
xbar_access_same_device_slow_rsp 1059.190s 97075.336us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 72.310s 2530.316us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 495.280s 18274.344us 100 100 100.00
xbar_stress_all_with_error 487.230s 19985.884us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 1175.540s 17418.381us 100 100 100.00
xbar_stress_all_with_reset_error 546.150s 18337.269us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 3664.160s 16644.916us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3451.850s 30787.406us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 3670.550s 16128.116us 3 3 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2644.330s 11017.787us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3513.060s 18045.781us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3506.550s 15741.767us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3558.490s 16308.167us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3357.240s 14947.360us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 21.560s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 25.670s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 22.250s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 19.250s 10.160us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 18.580s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 18.750s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 18.620s 10.340us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 20.930s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 22.370s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.750s 10.340us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.660s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.080s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.940s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 28.120s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.590s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.880s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.800s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.440s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.210s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.170s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.360s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.540s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.650s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.130s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.590s 10.120us 0 1 0.00
rom_e2e_asm_init 14 15 93.33
rom_e2e_asm_init_test_unlocked0 2725.820s 11819.634us 3 3 100.00
rom_e2e_asm_init_dev 3750.360s 15873.310us 2 3 66.67
rom_e2e_asm_init_prod 3794.270s 17036.297us 3 3 100.00
rom_e2e_asm_init_prod_end 3677.310s 14978.422us 3 3 100.00
rom_e2e_asm_init_rma 3390.180s 15397.237us 3 3 100.00
rom_e2e_keymgr_init 5 9 55.56
rom_e2e_keymgr_init_rom_ext_meas 6972.080s 28343.452us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_no_meas 7170.220s 30454.937us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_invalid_meas 7380.180s 29339.842us 1 3 33.33
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 3561.920s 15740.539us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3513.660s 34794.032us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3513.660s 34794.032us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 262.410s 3124.990us 3 3 100.00
chip_sw_aes_enc_jitter_en 187.590s 3399.598us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 237.650s 2706.271us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 245.300s 2717.712us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 2107.670s 12580.971us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 219.250s 2692.821us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 506.480s 5795.451us 3 3 100.00
chip_sw_all_escalation_resets 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 649.560s 5709.101us 3 3 100.00
chip_plic_all_irqs_10 350.050s 3501.854us 3 3 100.00
chip_plic_all_irqs_20 489.320s 4566.116us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 251.000s 3727.544us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1331.270s 12715.655us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 421.700s 5394.343us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 240.210s 3160.126us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1558.570s 8384.879us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1361.600s 8459.861us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1146.920s 8413.649us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11951.200s 254847.541us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 263.630s 4706.581us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 307.070s 5221.691us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 263.630s 4706.581us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 543.920s 7310.760us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_bite_reset 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 543.920s 7310.760us 1 3 33.33
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 486.410s 7804.269us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 441.200s 5293.323us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 789.380s 5996.288us 3 3 100.00
chip_sw_aes_idle 245.300s 2717.712us 3 3 100.00
chip_sw_hmac_enc_idle 234.270s 3438.422us 3 3 100.00
chip_sw_kmac_idle 209.940s 2834.105us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 367.180s 5014.061us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 272.160s 4115.464us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 260.710s 3521.649us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 345.570s 5246.494us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1087.950s 12745.653us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 527.200s 4300.161us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 513.250s 5156.795us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 495.770s 4265.882us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 482.500s 4552.876us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 519.030s 4579.427us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 470.550s 4960.078us 3 3 100.00
chip_sw_ast_clk_outputs 860.570s 8267.701us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 622.090s 12626.472us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 495.770s 4265.882us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 482.500s 4552.876us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 502.220s 4570.685us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 792.830s 5538.672us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4318.810s 19168.810us 3 3 100.00
chip_sw_aes_enc_jitter_en 187.590s 3399.598us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 878.020s 5972.980us 3 3 100.00
chip_sw_hmac_enc_jitter_en 178.560s 2863.873us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1407.460s 10233.231us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.730s 2929.972us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 458.800s 5076.650us 3 3 100.00
chip_sw_clkmgr_jitter 209.830s 2633.333us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 179.260s 2631.604us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 445.670s 4703.565us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 884.030s 6640.631us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4327.250s 24908.301us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 230.930s 3753.581us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 185.550s 3609.376us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1310.130s 11895.620us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 212.340s 2833.832us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 464.080s 5767.939us 3 3 100.00
chip_sw_flash_init_reduced_freq 1728.990s 23065.510us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 4513.140s 29127.385us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 860.570s 8267.701us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 495.150s 4732.446us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 353.740s 3626.825us 3 3 100.00
chip_sw_clkmgr_escalation_reset 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1558.570s 8384.879us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1316.780s 8549.549us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 3 33.33
chip_sw_csrng_fuse_en_sw_app_read_test 253.410s 4493.385us 1 3 33.33
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 530.700s 6697.227us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 223.430s 2976.240us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 5493.210s 23659.924us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 200.460s 2809.630us 3 3 100.00
chip_sw_edn_entropy_reqs 881.730s 6877.504us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 200.460s 2809.630us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1316.780s 8549.549us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 182.870s 2769.521us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1482.230s 19769.952us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 790.480s 5193.633us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 792.830s 5538.672us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 438.970s 3719.724us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 502.220s 4570.685us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4648.340s 43521.475us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1482.230s 19769.952us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 290.320s 4042.115us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4648.340s 43521.475us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_lc_seed_hw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_lc_escalate_en 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 225.250s 7649.120us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 617.080s 4337.173us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 463.300s 4351.446us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 463.300s 4351.446us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 186.640s 2880.198us 3 3 100.00
chip_sw_hmac_enc_jitter_en 178.560s 2863.873us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 234.270s 3438.422us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 1900.530s 11356.962us 3 3 100.00
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 893.050s 5814.859us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 528.390s 5286.144us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 440.450s 5106.944us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 540.890s 4629.665us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 380.280s 4140.308us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1407.460s 10233.231us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 1953.910s 11793.274us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 2107.670s 12580.971us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3466.070s 16162.015us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 216.040s 2715.394us 3 3 100.00
chip_sw_kmac_mode_kmac 281.470s 3203.465us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 235.730s 2929.972us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 224.910s 2746.532us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1653.460s 9952.625us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 209.940s 2834.105us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 506.480s 5795.451us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1133.370s 14922.301us 5 5 100.00
chip_tap_straps_rma 473.870s 6066.000us 5 5 100.00
chip_tap_straps_prod 972.970s 13538.470us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 224.370s 2960.156us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 1898.290s 11818.647us 3 3 100.00
chip_sw_lc_ctrl_broadcast 78 84 92.86
chip_prim_tl_access 225.250s 7649.120us 3 3 100.00
chip_rv_dm_lc_disabled 463.050s 14876.632us 0 3 0.00
chip_sw_flash_ctrl_lc_rw_en 370.640s 4147.698us 3 3 100.00
chip_sw_flash_rma_unlocked 4648.340s 43521.475us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 220.590s 3170.829us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 703.100s 7261.997us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 516.700s 5320.779us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 719.240s 7548.329us 0 3 0.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 453.090s 8590.302us 3 3 100.00
chip_sw_sram_ctrl_execution_main 875.480s 9948.304us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 622.090s 12626.472us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 527.200s 4300.161us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 513.250s 5156.795us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 495.770s 4265.882us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 482.500s 4552.876us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 519.030s 4579.427us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 470.550s 4960.078us 3 3 100.00
chip_tap_straps_dev 1133.370s 14922.301us 5 5 100.00
chip_tap_straps_rma 473.870s 6066.000us 5 5 100.00
chip_tap_straps_prod 972.970s 13538.470us 5 5 100.00
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 187.900s 3225.789us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 122.400s 2912.602us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 101.980s 2935.048us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 204.590s 3319.849us 3 3 100.00
chip_lc_test_locked 3 6 50.00
chip_rv_dm_lc_disabled 463.050s 14876.632us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 1969.990s 33759.556us 3 3 100.00
chip_sw_lc_walkthrough 15 15 100.00
chip_sw_lc_walkthrough_dev 5414.100s 48196.830us 3 3 100.00
chip_sw_lc_walkthrough_prod 5465.010s 50363.923us 3 3 100.00
chip_sw_lc_walkthrough_prodend 688.560s 9346.618us 3 3 100.00
chip_sw_lc_walkthrough_rma 5055.910s 46546.379us 3 3 100.00
chip_sw_lc_walkthrough_testunlocks 1969.990s 33759.556us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 93.630s 2350.116us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 87.200s 2504.045us 3 3 100.00
rom_volatile_raw_unlock 88.910s 2612.768us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4094.530s 16845.382us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4318.810s 19168.810us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 789.380s 5996.288us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 789.380s 5996.288us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 789.380s 5996.288us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 368.690s 3128.429us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 1482.230s 19769.952us 3 3 100.00
chip_sw_otbn_mem_scramble 368.690s 3128.429us 3 3 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 511.910s 4510.526us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.440s 2878.966us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 1482.230s 19769.952us 3 3 100.00
chip_sw_otbn_mem_scramble 368.690s 3128.429us 3 3 100.00
chip_sw_keymgr_key_derivation 1511.890s 10885.837us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 511.910s 4510.526us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.440s 2878.966us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 425.020s 4778.205us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 224.370s 2960.156us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_prim_tl_access 225.250s 7649.120us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 220.590s 3170.829us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 703.100s 7261.997us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 516.700s 5320.779us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 719.240s 7548.329us 0 3 0.00
chip_sw_lc_ctrl_transition 951.430s 12319.427us 15 15 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 225.250s 7649.120us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 930.410s 7100.102us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 376.410s 7413.483us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1324.720s 28052.750us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 381.570s 7469.274us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 439.690s 7911.407us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 515.970s 6600.530us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1356.640s 24553.508us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 6 33.33
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 964.290s 12866.263us 1 3 33.33
chip_sw_aon_timer_wdog_bite_reset 543.920s 7310.760us 1 3 33.33
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1212.530s 13473.607us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 385.430s 4547.016us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 376.410s 7413.483us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 425.200s 4957.723us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2 3 66.67
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2682.940s 31590.920us 2 3 66.67
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 446.920s 7117.762us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 450.260s 6927.861us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 2 3 66.67
chip_sw_pwrmgr_random_sleep_all_reset_reqs 2034.620s 21751.369us 2 3 66.67
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 808.870s 6318.066us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1113.260s 12364.342us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2164.230s 31889.793us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 256.890s 3278.672us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 453.090s 8590.302us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 453.090s 8590.302us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 11 12 91.67
chip_sw_pwrmgr_all_reset_reqs 1113.260s 12364.342us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 2034.620s 21751.369us 2 3 66.67
chip_sw_pwrmgr_wdog_reset 385.430s 4547.016us 3 3 100.00
chip_sw_pwrmgr_smoketest 307.070s 5221.691us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 322.610s 4053.365us 3 3 100.00
chip_sw_rstmgr_cpu_info 0 3 0.00
chip_sw_rstmgr_cpu_info 325.110s 3995.121us 0 3 0.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 340.850s 3482.158us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1331.270s 12715.655us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 216.540s 2597.572us 3 3 100.00
chip_sw_rstmgr_escalation_reset 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1361.600s 8459.861us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 636.560s 4779.819us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 658.950s 5064.650us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 200.560s 2448.783us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 188.440s 2878.966us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 0 3 0.00
chip_sw_rstmgr_cpu_info 325.110s 3995.121us 0 3 0.00
chip_sw_rv_core_ibex_double_fault 0 3 0.00
chip_sw_rstmgr_cpu_info 325.110s 3995.121us 0 3 0.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1854.500s 16373.569us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1283.080s 14029.954us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 322.610s 4053.365us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 223.770s 2290.865us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 363.190s 5480.654us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 473.870s 6066.000us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 463.050s 14876.632us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 649.560s 5709.101us 3 3 100.00
chip_plic_all_irqs_10 350.050s 3501.854us 3 3 100.00
chip_plic_all_irqs_20 489.320s 4566.116us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 178.640s 3099.665us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 210.530s 2992.514us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 3664.160s 16644.916us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 574.240s 7402.988us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 237.870s 3434.154us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 220.260s 3244.743us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 334.320s 3691.893us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 511.910s 4510.526us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 458.800s 5076.650us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 609.150s 6850.202us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 526.440s 8026.017us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 875.480s 9948.304us 3 3 100.00
chip_sw_sram_lc_escalation 97 106 91.51
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
chip_sw_data_integrity_escalation 617.340s 6170.122us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 808.870s 6318.066us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1423.390s 24897.315us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 209.110s 2847.925us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 284.910s 3618.008us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 435.160s 4731.975us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1423.390s 24897.315us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1423.390s 24897.315us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 2972.150s 19995.278us 2 3 66.67
chip_sw_sysrst_ctrl_flash_wp_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 2972.150s 19995.278us 2 3 66.67
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 406.120s 5537.679us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3513.660s 34794.032us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 118.590s 2798.366us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 135.750s 2977.881us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 289.700s 3670.381us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 390.910s 3604.220us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1310.910s 8164.484us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6216.660s 31616.460us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2110.740s 12024.716us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 167.990s 2355.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 247.850s 2662.161us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 198.840s 2198.077us 3 3 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 14944.970s 72086.631us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1362.180s 7053.077us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 173.980s 3975.186us 0 1 0.00
rom_e2e_jtag_debug_dev 209.910s 4219.816us 0 1 0.00
rom_e2e_jtag_debug_rma 530.650s 6491.478us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 76.770s 2329.496us 0 1 0.00
rom_e2e_jtag_inject_dev 63.240s 2355.363us 0 1 0.00
rom_e2e_jtag_inject_rma 106.310s 2430.918us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 58.491s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 3 3 100.00
chip_sw_clkmgr_jitter_frequency 709.890s 5999.476us 3 3 100.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 365.610s 2858.110us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1421.210s 7079.765us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1650.160s 8973.187us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 283.200s 2591.543us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 726.750s 5609.588us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 152.600s 2459.521us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 137.980s 2355.800us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 354.840s 5387.571us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 426.880s 5016.095us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1113.260s 12364.342us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 173.980s 3975.186us 0 1 0.00
rom_e2e_jtag_debug_dev 209.910s 4219.816us 0 1 0.00
rom_e2e_jtag_debug_rma 530.650s 6491.478us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 484.370s 4885.239us 3 3 100.00
chip_sw_plic_alerts 91 100 91.00
chip_sw_all_escalation_resets 578.810s 5379.399us 91 100 91.00
tick_configuration 1 3 33.33
chip_sw_rv_timer_systick_test 6933.790s 38516.783us 1 3 33.33
counter_wrap 1 3 33.33
chip_sw_rv_timer_systick_test 6933.790s 38516.783us 1 3 33.33
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 197.830s 4028.396us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 455.720s 4644.859us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3526.480s 19283.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 22 77.27
chip_sival_flash_info_access 207.260s 3270.342us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 402.810s 4138.867us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 85.810s 2512.703us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 190.340s 2571.770us 3 3 100.00
chip_sw_otp_ctrl_descrambling 222.100s 3109.274us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 291.740s 4146.632us 2 3 66.67
chip_sw_pwrmgr_sleep_wake_5_bug 14.101s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 261.770s 3677.743us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32068) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 37667621270960057770369001057559302473913897249655636611671036343337836738644 214
UVM_ERROR @ 2384.750352 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32068) { a_addr: 'h106ac a_data: 'h5f78d9f1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h1ae90 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2384.750352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 43304392577226336902830499402505053529699184011365389144095317174343543191535 282
UVM_ERROR @ 14876.632329 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105ec read out mismatch
UVM_INFO @ 14876.632329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 17375718791692794145428703911835181316630333616885474577003815691358127720857 212
UVM_ERROR @ 2563.754089 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10730 read out mismatch
UVM_INFO @ 2563.754089 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 7934102381012959958395037084893596566399136770435293578419264590811702735731 242
UVM_ERROR @ 8162.471863 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10790 read out mismatch
UVM_INFO @ 8162.471863 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31660) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 108462820040426753670010128988947258739062459069306402768247891072807660686781 221
UVM_ERROR @ 2614.129293 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31660) { a_addr: 'h10300 a_data: 'ha63f3b25 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h18ac0 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2614.129293 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36472) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 79977931399951956665420008159045648381767359015941441275640433325202643901476 214
UVM_ERROR @ 2772.349906 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36472) { a_addr: 'h104b0 a_data: 'h72c907fa a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h19909 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2772.349906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31640) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 82989207875782512423181672876056467017571866934878360650714516562034195264238 221
UVM_ERROR @ 2662.380944 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31640) { a_addr: 'h1046c a_data: 'hac2371be a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h1bd86 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2662.380944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31702) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 85370396900262088690361952264300292045231303261086655305094305797186875028648 214
UVM_ERROR @ 2103.504680 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31702) { a_addr: 'h105b0 a_data: 'hd3a8e09c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h19e5c d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2103.504680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32024) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 50711087040213850600222036141047156453308046157588296724237379502266514784543 221
UVM_ERROR @ 2792.108260 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32024) { a_addr: 'h10654 a_data: 'h70f2cb66 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h19e4b d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2792.108260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32904) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 85890183746996108637359712836005059671201232510451483978410220071468957298088 214
UVM_ERROR @ 2250.724921 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32904) { a_addr: 'h10430 a_data: 'h9b381405 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h1a9e1 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2250.724921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32514) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 101366300962856322564413147167262420681462859666092092951185967019010703644566 214
UVM_ERROR @ 2360.101368 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32514) { a_addr: 'h10798 a_data: 'he0600a47 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h4 a_user: 'h1990a d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2360.101368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34730) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 19530610898364666285040925611690275650838334462287883791176777922536325117023 214
UVM_ERROR @ 2267.345574 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34730) { a_addr: 'h10578 a_data: 'h6757cfe0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h192a8 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2267.345574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32236) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 59046411102962858441247096421768612638661969221167869958373780909058033388324 214
UVM_ERROR @ 2922.474931 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32236) { a_addr: 'h10724 a_data: 'h706589fb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h18dc7 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2922.474931 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37302) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 107546143761322503004801481978988819856309324802766786027052007001643972150693 214
UVM_ERROR @ 2928.261864 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37302) { a_addr: 'h1051c a_data: 'h367b8710 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1ae59 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2928.261864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32576) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 40853542354180567189709705377932308323768817008367479083782980222089476045692 221
UVM_ERROR @ 2381.526941 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32576) { a_addr: 'h10438 a_data: 'hf619192b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h1bd34 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2381.526941 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32766) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 72357835379848631066173001527319288412094340300376706594636306721813451320926 214
UVM_ERROR @ 2613.782292 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32766) { a_addr: 'h1078c a_data: 'heef9c9c5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h1b11c d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2613.782292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32062) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 25634082679159462855992303831101802315039582418737141061484477125105101500799 221
UVM_ERROR @ 2599.508478 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32062) { a_addr: 'h104d8 a_data: 'hf4f6b7d6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h1bd90 d_param: 'h0 d_source: 'h3d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2599.508478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32590) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 54561402100048434699049488771240992869327107401611953692678134758470843114729 221
UVM_ERROR @ 2892.258846 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32590) { a_addr: 'h106c0 a_data: 'h983ecd46 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h186e1 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2892.258846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31852) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 86813985309123476405486116135899533095899936577040746749623623647612743165603 214
UVM_ERROR @ 3134.457614 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31852) { a_addr: 'h1060c a_data: 'h7668897d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h18691 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3134.457614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31578) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 26496736308284937808293796263994601005462419026198711782503395521036920296775 221
UVM_ERROR @ 2331.305830 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31578) { a_addr: 'h10434 a_data: 'h91cbca80 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h1a57b d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2331.305830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39816) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 104982104976218517032082433349956411514601860847686559089647717799337287107480 214
UVM_ERROR @ 2513.137640 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39816) { a_addr: 'h1055c a_data: 'hf1506216 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h186d9 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2513.137640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31532) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 24156910904364476651949862551170866594243985117854675360782769738233067075518 221
UVM_ERROR @ 1896.861806 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31532) { a_addr: 'h10660 a_data: 'h5fe0a8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h4 a_user: 'h1aebb d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1896.861806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39374) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 105129482815078124345421467118283520733598772999954837786862927368353791675876 214
UVM_ERROR @ 2700.620160 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39374) { a_addr: 'h10744 a_data: 'hf72c912b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1bde3 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2700.620160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32448) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 58814722255456006831889471093893735412864819351800266785059873157032305210653 214
UVM_ERROR @ 2023.354955 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32448) { a_addr: 'h104c0 a_data: 'h2f7d9233 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h18df6 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2023.354955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 30904345698823868534888341489558543479287421457263039179915937472888204262541 221
UVM_ERROR @ 2979.595200 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32448) { a_addr: 'h106c8 a_data: 'hd985917a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h19237 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2979.595200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31902) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 695252080586325186723931052456406282060092960496430078705267301645257216276 214
UVM_ERROR @ 1938.406570 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31902) { a_addr: 'h104a0 a_data: 'h3f2c3d06 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1bdee d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1938.406570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32260) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 39685879161652601907254361106367867367488678643518671131719043014251065715500 221
UVM_ERROR @ 2347.951376 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32260) { a_addr: 'h104f8 a_data: 'h6c38c415 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h28 a_opcode: 'h4 a_user: 'h1a57e d_param: 'h0 d_source: 'h28 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2347.951376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32834) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 68443562059085613597423343644393871466619560122367729168109791173586066625348 214
UVM_ERROR @ 2883.047816 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32834) { a_addr: 'h10520 a_data: 'hb27e3a93 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h18a76 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2883.047816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32930) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 9241903703038935525285733104599725619366879177955747377186526283259032209160 221
UVM_ERROR @ 1709.162789 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32930) { a_addr: 'h106d0 a_data: 'h474bf917 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h1a210 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1709.162789 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35336) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 34557632969302414638560148312708941820167912352917546595177095031538905015158 214
UVM_ERROR @ 2042.491333 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35336) { a_addr: 'h105e4 a_data: 'h5ed77cb9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h19eb0 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2042.491333 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41290) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 8295394836936787897152185199899711606381633650327287023251341191668274045953 214
UVM_ERROR @ 2686.182562 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41290) { a_addr: 'h10580 a_data: 'h2f792f1f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1a275 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2686.182562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31800) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 26558317317168578503479845331375021076077188333013018381865844574766567797201 221
UVM_ERROR @ 2839.701122 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31800) { a_addr: 'h10624 a_data: 'hf2e4d4ae a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h18ad8 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2839.701122 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34514) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 17700284594081091985631045621084552767668333354529223567861690804417284020241 214
UVM_ERROR @ 2444.641336 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34514) { a_addr: 'h10368 a_data: 'h5e96ba4c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1ae53 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2444.641336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40780) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 83613129220530241060963262891784573069668834894880719189258562272117725019450 214
UVM_ERROR @ 2743.604804 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40780) { a_addr: 'h105bc a_data: 'h53ca3f5c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1861a d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2743.604804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36260) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 54335149626926381283445586944472584091983866042825170201529147894062781393414 223
UVM_ERROR @ 2383.700939 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36260) { a_addr: 'h1000 a_data: 'hd9754556 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hb a_opcode: 'h0 a_user: 'h2400a d_param: 'h0 d_source: 'hb d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2383.700939 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31644) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 21892171893003116728117749796939316223732001033488289189867406619852286217259 214
UVM_ERROR @ 2694.544754 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31644) { a_addr: 'h106e8 a_data: 'hcf79a3e5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h18ad2 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2694.544754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@144014) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 43847179915679719134945846352237269272975044296451253832641984153478778518445 215
UVM_ERROR @ 3209.003184 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@144014) { a_addr: 'h10614 a_data: 'h50b3e614 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1b6cf d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3209.003184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32736) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 85943473837726775400714943892122724876978559949245687568556974993210504405816 214
UVM_ERROR @ 2057.158458 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32736) { a_addr: 'h10118 a_data: 'h15577697 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1b1e8 d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2057.158458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31894) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 86225543306750672996746022478843528234582647359728220508958279444012767211203 214
UVM_ERROR @ 2019.344040 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31894) { a_addr: 'h104e0 a_data: 'hd04c386b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h1957c d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2019.344040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32474) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 44124290710526060111353877107436842753114588550237637089166908564984032244100 214
UVM_ERROR @ 1939.262444 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32474) { a_addr: 'h10360 a_data: 'ha781a5cd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1baf3 d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1939.262444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31472) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 6199217553845343026369200246335705175829419498524532386901388302114957436073 214
UVM_ERROR @ 2329.421616 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31472) { a_addr: 'h104b8 a_data: 'h9ba5c922 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h18d8c d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2329.421616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33944) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 60325582528719370467256700971415430582051747373691356857192805194018893622540 214
UVM_ERROR @ 1897.437194 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33944) { a_addr: 'h10578 a_data: 'h934bc97 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h192d0 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1897.437194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34580) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 6097147635595856007031379034519412592555768073483176796546998907446400159720 214
UVM_ERROR @ 2362.207500 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34580) { a_addr: 'h10538 a_data: 'h5cf97d4c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1ba71 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2362.207500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 73248716916031998587777526561371928402423487184395702786560467508540254394559 641
UVM_ERROR @ 3462.335000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3462.335000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_mio_dio_val 33654047928540286455808008950265988467036666935902272813280663081919540715852 533
UVM_ERROR @ 3363.070000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3363.070000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 38425661860400389314121353636171705783604407816967938435363015426768466512139 618
UVM_ERROR @ 3051.879287 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3051.879287 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 21466330557065599804275736927611306335983814786789058725771899380452197734948 402
UVM_ERROR @ 3508.437600 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3508.437600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 9835892377679866624614820983580665850006089997155438773755880850325704457762 562
UVM_ERROR @ 7548.329209 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7548.329209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 107210706292544747071765017591682520854927982832974163393607078253417106479655 421
UVM_ERROR @ 4530.592600 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 4530.592600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 109528961965800316487745423661023688151307963353238270497427559657009914373266 424
UVM_ERROR @ 6255.569379 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6255.569379 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 19090425267167502669252533037480704803571254518516084944995142335860026385121 570
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2355.800072 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2355.800072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 24675111288635210043114575621560783648875917917330476667560234933581058475462 396
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2966.894680 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2966.894680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 82148150176511710086320680264870718281528184395413798973712421619698028251329 394
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3176.779560 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3176.779560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 26557795148054613556052117238322723178015077748854800225117812575995418335499 395
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3204.482952 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3204.482952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 84914477267067386106361371976714389433164527470533017440388225063017951282695 399
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3506.303292 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3506.303292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 53725994332914003207212903400690471300998899299287076415938348329884732677479 404
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3044.231552 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3044.231552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 104969690052230161013005669740783408043325896112617339010113038465025422271867 494
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 31304033612458103839855403788073088737771052655828269032937223659520655835939 419
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 55317077706642201771478766911199272347343123408004548465412232968156597440429 534
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 89406973971012817437267864724418838797483628772507966957886496739496247026005 535
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 6290563807650411256207174107373465994191047706346606950440272041332688735633 615
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 37834209167169894538361187718474228097098683707843591157995305874646985258306 487
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 61217785571409447892401420033948595626337308062228402930452214529080526624455 483
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 41673285049992472212808340934223682870214000683603961178009026326832170188097 545
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 57568352009885446266642377949481209871117502199225202395700798903181662934525 411
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 71619622387855629534862043187279300351610721948918246531119603686856191122931 409
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86876) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 52414722103097739965985145281592906759869077783372825495157879863875569272256 412
UVM_ERROR @ 4093.394490 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@86876) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4093.394490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 114676880500960432012326170593750061648466100409342950318028377395062096838470 434
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5583.580000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5583.580000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 102342686822766297770133319621035974374362414692887051124143471019411124511202 427
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5598.112000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5598.112000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 79813309990045046034052381393154576937110992740553394484725078248982435358015 431
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7911.407000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7911.407000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 23205519429822144260351389413106036921136503463750200543066493201107168622126 461
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 18664.375000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 18664.375000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 41019363355053573549566652028504966757271105785370770040423671614528027947743 413
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6582.505000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6582.505000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 55761036876528673204407654233706026568281090737669841985240171658992140053045 400
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 6624.797000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6624.797000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 29985538523540114005987377473492267475855285979724728747487703002083602487873 396
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5648.013000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5648.013000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 420558109706086545502859896867321328411431777906040439924503904234881201020 406
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7776.475000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7776.475000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 29006138577343939546185267702414978759391168459627809600961678348001324705317 400
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7501.757500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7501.757500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_rv_timer_systick_test 96161344769622994672359320716094634013936164562621669251024541910595587268204 None
Job timed out after 120 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 81207051131050730414206520755999807082359682147473068605385128933139023789206 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 9032979264031588156905852390448091591999179591742487001894739911392927911626 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 10015396570849660248398955673214564362795572592575735858632424970314407721739 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 794180311866114959171007804854990802923062514756847193233161775818520528734 None
Job timed out after 240 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 105589655812504931802354707059470012522723195658093126810455156371287268235527 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 45400306961027796752246805787989708231481524454180052766295279275802153637515 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 70401509099687616131907204606992169735126983650936205962881892842752497755328 414
UVM_ERROR @ 34794.031525 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34794.031525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 31385937144081875868034082709011344274104662350604305093033064533229427351115 406
UVM_ERROR @ 2510.673337 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 2510.673337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 107966642617266627586467935675381304604374344116320920482918214077551022382317 389
UVM_ERROR @ 3010.525024 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 3010.525024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 43662797958186455305693010510537267012679020477188090387310585716011832262535 391
UVM_ERROR @ 2691.512485 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2691.512485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106843134124179589911281910154557181364307824732557080792273705408933371958057 390
UVM_ERROR @ 2893.881768 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2893.881768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102889494833547990717763592283086909496398673737512773045213154246079577745669 394
UVM_ERROR @ 2482.599765 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2482.599765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20955724112885922559375906801511756186168831835097027802054324063136114377827 390
UVM_ERROR @ 2979.522130 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2979.522130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62000762111578323811295629704818594649994239245339402688323565191240149834138 390
UVM_ERROR @ 2271.528038 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2271.528038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 110360159949339858469544839310458376911549407983895533754982051393180001758672 390
UVM_ERROR @ 3053.928318 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3053.928318 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88204831129473202449484323711043735049458741783494977320080965146665173996401 390
UVM_ERROR @ 2978.712146 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2978.712146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8912799218109944207433749701078920096004166776897801032914989723564544692182 390
UVM_ERROR @ 2490.733300 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2490.733300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 30923331531631270400845392713441259851111075175549060346691267163123980062250 390
UVM_ERROR @ 2783.386252 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2783.386252 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 103126575982591022005069902603551182527145482077930982694706553676679652461630 390
UVM_ERROR @ 2149.432076 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2149.432076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13663387505250650928299497712260552857996656309480662031548090662580670438062 390
UVM_ERROR @ 2324.131996 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2324.131996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35036742241666722375193855235721779953867614984505608003881535538684467032898 390
UVM_ERROR @ 2928.050912 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2928.050912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94439604508416140122944909787083287061509320897147074404216240720448240894064 390
UVM_ERROR @ 3021.994056 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3021.994056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23915187499423992612931018221514599957728863846371914386460595044490464010772 390
UVM_ERROR @ 3429.495825 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3429.495825 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82728752149897426849110914727323788589204167756123203166744114625435762238284 392
UVM_ERROR @ 3249.717875 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3249.717875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81947017369453080191448437168127441781156008151860831393369530528981901558998 390
UVM_ERROR @ 3423.549554 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3423.549554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12369484019560564492456053737751177839501416854919265342497107390171223856809 399
UVM_ERROR @ 2897.244584 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2897.244584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14425420188670362719566850913948963396459298348835750570484954815303695106687 391
UVM_ERROR @ 3282.907608 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3282.907608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43395384346727064740132178383082983094840421252200267875173377002780489066065 390
UVM_ERROR @ 2970.963313 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2970.963313 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65796519624439555095967366033565124547071266562644009545944635844219449598852 390
UVM_ERROR @ 2785.835110 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2785.835110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39494892198030786958567791058020455753297262074939577148150252158455580371301 385
UVM_ERROR @ 2227.303655 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2227.303655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4538083708136241952574688566179384421641751876646018244784964898982661722347 390
UVM_ERROR @ 2670.031960 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2670.031960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93356462172004290564108328635589796447484966590965129577421209718482185569714 390
UVM_ERROR @ 3022.933440 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3022.933440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61656926339471169362395220375435522651118109591741596345549429204028793020420 389
UVM_ERROR @ 2642.904325 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2642.904325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79558319290828761895603282468515544005738575488554887355377008899714778371790 390
UVM_ERROR @ 3160.126076 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3160.126076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55224760404989583394073127076764315261307272103877053404919376663024466425149 396
UVM_ERROR @ 2392.322888 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2392.322888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23505234102024618267791085368490264080526990360133766788027255641046206129570 390
UVM_ERROR @ 3299.737801 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3299.737801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 25461533434250397933501071438235256260420558299371347315281828586748212332882 392
UVM_ERROR @ 2474.433080 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2474.433080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90478433314255068562474330726989021993336235715780730647756913159375885537404 392
UVM_ERROR @ 2849.502810 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2849.502810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27732983793369159828928254161063597534376552255775756465429700871678014056957 390
UVM_ERROR @ 2556.797368 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2556.797368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35207429301601789310044677023532356239858849203455165346087837745406248012232 401
UVM_ERROR @ 2600.366686 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2600.366686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3405368221630521519931354478696157534228414072988419083356558661538587374418 401
UVM_ERROR @ 2543.612264 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2543.612264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 48629305283095094726607893186062972313295264850834427889682185318168714246534 394
UVM_ERROR @ 2837.351285 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2837.351285 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51900097894452663156450067968684308837553141510556264031825854240169987302772 396
UVM_ERROR @ 3054.795226 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3054.795226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6965772093998756514363856741041265017068299967534975997075250234190348565629 393
UVM_ERROR @ 2424.144900 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2424.144900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20899552342025927712310890449098785007580641851491967714397341749851591807778 400
UVM_ERROR @ 2338.081536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2338.081536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47248112320717275202295422786547100006650092957131155519989788679648380749343 407
UVM_ERROR @ 2952.991776 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2952.991776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78955125790271356347581746016189467857168358633696187131167742345916211188912 408
UVM_ERROR @ 2910.027440 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2910.027440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36162763835158089248293652993038737754598035690103358615217442673800590184306 393
UVM_ERROR @ 3188.593056 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3188.593056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80844814008440704083857235330163636254588429797871043884554024753011420363190 397
UVM_ERROR @ 1981.849690 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 1981.849690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78315134191331349733136984743443152294043836398614895473595288236430524630786 390
UVM_ERROR @ 2630.890744 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2630.890744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46856239805321378978202356954446860297172611559387341282822826739382102176199 393
UVM_ERROR @ 3516.565359 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3516.565359 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40084558597506766395513752746115207594937967645894896864677555608779690616441 398
UVM_ERROR @ 2808.457472 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2808.457472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 52460178432206160530584113786898958394588846188539190407722054250044335119797 397
UVM_ERROR @ 3098.657349 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3098.657349 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107934002465152398664375121091654912942506698715493563999211093738364005512454 385
UVM_ERROR @ 2131.819719 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2131.819719 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36614296710360936253771094125277370022182886808538867677242085291668274341776 390
UVM_ERROR @ 2796.825505 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2796.825505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3997354820702915662337522325184671031978972978426203642909589359626763992162 390
UVM_ERROR @ 2203.521456 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2203.521456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41246964529060332832611441489731887227791842145233257925101241266786645306865 392
UVM_ERROR @ 2576.056412 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2576.056412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40767207866367582439483495933347531985975796196617184196874801426959145724060 398
UVM_ERROR @ 3072.679020 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3072.679020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34874218369117066871079624403693978510344544704941655286021236108077098050184 395
UVM_ERROR @ 2960.593460 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2960.593460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6850700764711590292377153004747417363234435357608989817210620310258210590727 390
UVM_ERROR @ 3181.061416 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3181.061416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62261634562119809676708838105268480090483948396795049419587473583924598153778 396
UVM_ERROR @ 2103.826000 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2103.826000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31834547426593974473879147970283523072455598967018331781306277068863460450585 390
UVM_ERROR @ 2146.199610 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2146.199610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3539436214324723826577461184830340127484669501225390140062762119081667654891 397
UVM_ERROR @ 2050.734424 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2050.734424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106375966370768582664357373953564191501676803156920474118588524284523337015418 389
UVM_ERROR @ 2446.560947 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2446.560947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68884939908986583577612249009016977828101614801544849432763232312395494707585 389
UVM_ERROR @ 2992.370000 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2992.370000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26226963251782049791883873711232206773380903721101547685704088333084429022919 390
UVM_ERROR @ 3022.003255 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3022.003255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41160311669939314979592948308992113772556307628682586356476826990028739420501 394
UVM_ERROR @ 2790.194150 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2790.194150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35755023632437970974608797561460027131514374134315692587203927351976096238944 392
UVM_ERROR @ 2724.003303 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2724.003303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17409545414960585758099617864583726829891755592810099630591711060265742579189 390
UVM_ERROR @ 2736.463698 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2736.463698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47451554683665408983483537078881016119463393012400067457028846372580850420016 389
UVM_ERROR @ 2479.328094 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2479.328094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 112422699693373102077967177220803463148006845612389379566925288143860521270424 390
UVM_ERROR @ 2695.890314 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2695.890314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77742009970261736515415743935263550248343419977288166786187115893206078206792 403
UVM_ERROR @ 3091.737549 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3091.737549 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108836245116021690530380360284223082642908854091571385825398854552132849355346 400
UVM_ERROR @ 3364.952991 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3364.952991 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16603054660826206119524651463697434679209778560976622769235893878559639713382 396
UVM_ERROR @ 3081.521336 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3081.521336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57112049600492086625744588197973043331518639450925800911499965796390258417333 390
UVM_ERROR @ 3025.610760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3025.610760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81204163705086398000535207952527622646751280016561247407229234134797721124267 390
UVM_ERROR @ 2790.533229 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2790.533229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40177285451939183312016072833090700997462359229664279051878092904393539673856 390
UVM_ERROR @ 2756.668920 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2756.668920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2057568455236606106970380411015088437451706402572291686628838536433779709115 390
UVM_ERROR @ 2446.336821 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2446.336821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62384728790950247698038557041085317089121589729844687005213123033600800549865 391
UVM_ERROR @ 2602.859598 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2602.859598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1361529916593909248558738228365884490901252294704806635756555925668078577978 395
UVM_ERROR @ 2521.794400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2521.794400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69020121359359118630966688299568351783651741417986946012803227539638501217405 394
UVM_ERROR @ 2763.399366 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2763.399366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 47748102938214222965508428468594334854074226070110207550186545053474609766249 390
UVM_ERROR @ 2871.228643 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2871.228643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 154651363185215415069261809258697832669869185690809389401501304030180594732 395
UVM_ERROR @ 2938.557921 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2938.557921 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 99704182257125460524485470326966805358152744186734709455693201171778464219292 398
UVM_ERROR @ 2990.775870 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2990.775870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 49178804811629776101773204048316279687595791762709768121846198975049153067417 393
UVM_ERROR @ 2671.251927 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2671.251927 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 105493520175746124643834689517845343920846566873380020109189325653378029802877 399
UVM_ERROR @ 3138.058576 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3138.058576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69968289930320424499135133396637294690157497672885487087591226357656710357447 389
UVM_ERROR @ 2504.861932 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2504.861932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40851251012614318342135689855505451184816591338901074536727262708587005272429 390
UVM_ERROR @ 2913.162169 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2913.162169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78642490716025806356655449144024775467489119273690689635263683447384378575478 404
UVM_ERROR @ 3309.557672 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3309.557672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 72859404379028739659370723908693185440440080733293917454958060963240253593497 399
UVM_ERROR @ 2083.562205 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2083.562205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7358445762457125995365802292428424027210251931425434841356235905930916807314 394
UVM_ERROR @ 2456.300996 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2456.300996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3239064027836446953906988332733047651455390229291765283777558511054497700791 399
UVM_ERROR @ 3115.675377 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3115.675377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107712344751276792446214540876865802100146499300294490917898004998633623502814 406
UVM_ERROR @ 2660.471816 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2660.471816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36422663829328480260790381035169737621154650054267996370441854591420612797760 406
UVM_ERROR @ 2404.380435 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2404.380435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 108267082439757172892037284910999598221176503167950488284951064560579140804604 400
UVM_ERROR @ 2295.410253 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2295.410253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73722848720129425114459167955008132396373302055344728211220725439857664405230 396
UVM_ERROR @ 3160.415294 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3160.415294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35827988161461532975835296104313932876606363312205185535479006368244600071549 390
UVM_ERROR @ 3542.412533 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3542.412533 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104775578932791933291339474818461432109928451223875601919316270311955550712994 397
UVM_ERROR @ 2585.863008 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2585.863008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 21195229849753442818194058416950976477631793588600247667360939899946116504435 393
UVM_ERROR @ 3114.258072 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3114.258072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 4749899307430607531584232739628003014517323470969354212896547804046924506946 394
UVM_ERROR @ 2852.864620 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 2852.864620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 33234728052734502268325101707183938634508852298777101206547568976968007363127 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.205s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 60700376347607243819069156272863984240459169412126853088861615523149099202726 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 48.641s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 111095737702235417399443894225680364344995727385785095046328067549981317670356 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.437s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 69221913708395059306210006334121209593336276180795936670394237485268946109096 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.196s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 95539491441663696621917625924808451559047557881391014564461127175063480410479 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.254s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 39869101072305088377785778150813388408892813532700420574716755595398225087461 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.228s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 59554286654511378188507342876374404497226930332778467689719755099464285755667 398
UVM_ERROR @ 3954.930000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3954.930000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 112180604115749377851521197499922865275765071389401371523529098189690183927226 395
UVM_ERROR @ 3255.784000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3255.784000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 114322682613795612003737735994987099618370525182158691917166944995600544354074 407
UVM_ERROR @ 3767.768000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3767.768000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 95635181233209234784194784319576890736236384509020858921856335700625179769637 410
UVM_ERROR @ 3095.651000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3095.651000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 39748581707782349153105766314843007791619280190036181204723650080974606534118 406
UVM_ERROR @ 3326.390000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3326.390000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 72150216939115844167119372983962244629901900108379907136072943656955113498446 412
UVM_ERROR @ 3207.844000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3207.844000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 12601405634526656774805111772911480588794673765523624929603745163790144254488 435
UVM_ERROR @ 14912.207781 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 14912.207781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 6760917118788444961281430251137506688064143142828705985662516167258265290344 429
UVM_ERROR @ 14843.019180 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 14843.019180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 24515179433424736568194468381174469794016797648416706649985760102796084023248 608
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 22052676514414587738732650465299979115442017531660562015600688352429991614429 561
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 24750314654693570212922168815858556837856096942829385963212419541337675657659 614
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 106315024322283129469890679001125009653619705065403545724004004818658229420874 596
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 26798838257362681080228834830662055333729076009558989746632889770609438899306 564
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 10583134119248506616974462119513790702107039886191813875724237677016775273920 555
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 34953801148129663823368784248055688393038591591499911707878894877476852519349 570
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 15836957217907953912667024086881765469391408120407393288746686722670807465181 559
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 52926496027669022297995200478480827511681006523549379057706114744449757185718 635
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 63343026594062783876118285408287922392573205169157552168814184079644365254454 753
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 113687032792106114623815373907213931749230298782532677601367017599371426159788 627
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 52279216950552986917720704356390416834041052650664861315321891027399732783065 893
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 113029230708161913412643248873143125972944951651423383840342501555611625747629 729
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 55414602752997659879087768171353407911854449608636323499478766721247966566962 625
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 6487504184477228438467958176429339942895136006955932435807502583875702086332 702
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 38920013837956915787731749244338746684645980942230959315835934662812452730823 629
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 64534617592871697669486649681277639877110317822057595612886850411111614960442 697
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 77076977370686593841823187919820618486397880066443755285826510069926298531038 596
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 57001778826521120477788868372420883165004872848578375103082021682922792045554 786
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 24168562466869849934250555560862013861208422161802612792452016020530414474326 553
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 87814715447196646128112719065642928816919053736676252810174714379579957257363 631
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 67397505936825755115058912544995952055705718360918853670104487546723724930329 791
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 64539307655459627267303842178926928755304802068105979377094883970645905520415 601
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 96181189738042218495588221354157900966693352171490815996125592756270752402194 637
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19934338223190921389736158715084055072584066509755081503378503904093217415344 617
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 66497139376806735099803765580093454645632321348125048206791760497696935354297 406
UVM_ERROR @ 3434.154143 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106764) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 72867893981062054434312373908978080162259749728559691203210272967932053497401 419
UVM_ERROR @ 3847.179640 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106764) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3847.179640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 6065912472153178578027714507940591442296725809972648955763110515843505067782 400
UVM_ERROR @ 11912.409980 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 11912.409980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 89265539746697527595824316927641757027873596660880096536819341719780159394108 398
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 2489.438224 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2489.438224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sensor_ctrl_alert 29759692409172058829863055379203794552279969179957578874237983143192380205293 398
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 2878.548624 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2878.548624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
rom_e2e_asm_init_dev 41945176154291883638835010965827500429047927578690483759566780245128663361712 427
UVM_FATAL @ 10010.120001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 30678470073142716240686438643220882448080229424764463420743174719901906426853 411
UVM_ERROR @ 16409.280600 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16409.280600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 4796521623473049237389691585494158850062397463409642238614334591965756608131 415
UVM_ERROR @ 16443.966200 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16443.966200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_keymgr_init_rom_ext_invalid_meas 81562802252454069940960971785527377233864899898478915245468568226216165063021 411
UVM_ERROR @ 19555.824000 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 19555.824000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@103404) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 114713347725026916806136752575452360957178133231314502657448524752487845756075 415
UVM_ERROR @ 3995.120976 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@103404) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3995.120976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *!
chip_sw_alert_test 8026500566448298037881372204852323112285239753812594837708999995727426612771 389
UVM_ERROR @ 2692.821093 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 31!
UVM_INFO @ 2692.821093 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 106952632506624048104534790941824856441775948943451943085739942372876489284356 415
UVM_ERROR @ 18358.009705 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 18358.009705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
chip_sw_all_escalation_resets 32820395090705226896979105072173864828754810575245742161448072551871449460165 397
UVM_ERROR @ 2627.768808 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2627.768808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 10515948444744165426711101059644305333133485199995630284901414848136939097295 400
UVM_ERROR @ 3514.184614 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3514.184614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 48503163050918973724109852462095290146478962011052144492781547344235206795374 398
UVM_ERROR @ 2685.220196 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2685.220196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 37430534918746444243893682927777097441494813909392414682030737259951676837585 410
UVM_ERROR @ 2633.939660 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2633.939660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 60023822369234765738908681247324708523146089365661703891456328581114463746544 402
UVM_ERROR @ 3159.910164 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3159.910164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 106794641669301687597698998621128475931999943182537129403190163101329943253881 400
UVM_ERROR @ 3341.286968 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3341.286968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---