clkmgr Simulation Results

Simulation Results: clkmgr

04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
98.95 %

assert
96.47 %

func
87.82 %

line
99.34 %

branch
99.17 %

cond
96.26 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		98.46%
V3		100.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	1.520s	111.809us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	0.900s	85.330us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	6.690s	1423.856us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	3.190s	963.530us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.470s	230.169us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
	clkmgr_csr_aliasing	3.190s	963.530us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.340s	156.549us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.970s	624.278us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	1.420s	90.904us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	1.150s	28.800us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	1.520s	111.809us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	12.870s	2476.681us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	12.800s	2178.250us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	12.870s	2476.681us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	59.470s	12314.679us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.420s	90.476us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	3.830s	778.181us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	3.830s	778.181us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	0.900s	85.330us	5	5	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
	clkmgr_csr_aliasing	3.190s	963.530us	5	5	100.00
	clkmgr_same_csr_outstanding	1.550s	295.714us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	0.900s	85.330us	5	5	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
	clkmgr_csr_aliasing	3.190s	963.530us	5	5	100.00
	clkmgr_same_csr_outstanding	1.550s	295.714us	20	20	100.00

V2S

576/585 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				23	25	92.00
	clkmgr_sec_cm	2.040s	361.548us	3	5	60.00
	clkmgr_tl_intg_err	2.470s	407.786us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.090s	286.953us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	2.090s	286.953us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	2.090s	286.953us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	2.090s	286.953us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	3.250s	603.962us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	2.470s	407.786us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	12.870s	2476.681us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	12.800s	2178.250us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	2.090s	286.953us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	1.390s	46.212us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.320s	202.196us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.440s	92.517us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				47	50	94.00
	clkmgr_clk_handshake_intersig_mubi	1.390s	279.452us	47	50	94.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.330s	48.933us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
sec_cm_idle_ctr_redun				3	5	60.00
	clkmgr_sec_cm	2.040s	361.548us	3	5	60.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	0.960s	22.063us	20	20	100.00
prim_count_check				3	5	60.00
	clkmgr_sec_cm	2.040s	361.548us	3	5	60.00

100/100 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	7.670s	1972.835us	50	50	100.00
stress_all_with_rand_reset				50	50	100.00
	clkmgr_stress_all_with_rand_reset	91.570s	29441.106us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	18418081047107291661925343582251974968868917541791074272241881418941045099647	83	UVM_ERROR @ 17081505 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 17081505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	70881276179917244040168416640040530852172075918602175134177167490384893185877	74	UVM_ERROR @ 3246309 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 3246309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	46456604392165950525947982686746697967197426683523668716309713162967871187791	71	UVM_ERROR @ 4851283 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (2 [0x2] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 4851283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	61379597455477251052312686720308024994005922072184914656355554948042833052136	71	UVM_ERROR @ 15750084 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (1 [0x1] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 15750084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	4021592305884536296303463024387508190482352396932564228589653443698022938478	71	UVM_ERROR @ 16033675 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (11 [0xb] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 16033675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---